743844-015.pdf - 第146页

The PCI Express* Host Bridge is required to translate the memory -mapped PCI Express* configuration space accesses from the host processor to PCI Express* configuration cycles. T o maintain compatibility with PCI configu…

PCI Express* Architecture

Compatibility with the PCI addressing model is maintained to ensure that all existing

applications and drivers operate unchanged.

The PCI Express* configuration uses standard mechanisms as defined in the PCI Plug-

and-Play specification.

The processor PCI Express* port supports Gen 4 at 16GT/s uses a 128b/130b

encoding and Gen 5 at 32 GT/s uses a 128b/130b encoding

S/HX/S Refresh/HX Refresh/E/E Refresh-Processor Line: The 4 lanes port can

operate at 2.5 GT/s, 5 GT/s, 8 GT/s or 16 GT/s.

S/HX/S Refresh/HX Refresh/E/E Refresh-Processor Line: The 16 lanes port

can operate at 2.5 GT/s, 5 GT/s, 8 GT/s, 16 GT/s or 32 GT/s**

H/H Refresh/P/PX/U/U Refresh -Processor Line: Each of the 4 lanes ports can

operate at 2.5 GT/s, 5 GT/s, 8 GT/s or 16 GT/s.

H/H Refresh-Processor Line: The 8 lane port can operate at 2.5 GT/s, 5 GT/s, 8

GT/s, 16 GT/s or 32 GT/s**

PX-Processor Line: The 8 lane port can operate at 2.5 GT/s, 5 GT/s, 8 GT/s, or 16

GT/s**

The PCI Express* architecture is specified in three layers – Transaction Layer, Data

Link Layer, and Physical Layer. Refer to the PCI Express Base Specification 5.0 for

details of PCI Express* architecture.

PCI Express* Configuration Mechanism

The PCI Express* (external graphics) link is mapped through a PCI-to-PCI bridge

structure.

Figure 21. PCI Express* Related Register Structures in the Processor

PCI-PCI Bridge

representing

root PCI

Express* ports

(Device 1)

PCI Compatible

Host Bridge

Device

(Device 0)

PCI

Express*

Device

PEG

DMI

7.1.2

7.1.3

PCIe* Interface—Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

May 2025 Datasheet, Volume 1 of 2

Doc. No.: 743844, Rev.: 015 145

The PCI Express* Host Bridge is required to translate the memory-mapped PCI

Express* configuration space accesses from the host processor to PCI Express*

configuration cycles. To maintain compatibility with PCI configuration addressing

mechanisms, it is recommended that system software access the enhanced

configuration space using 32-bit operations (32-bit aligned) only. Refer to the PCI

Express Base Specification for details of both the PCI-compatible and PCI Express*

Enhanced configuration mechanisms and transaction rules.

PCI Express* Equalization Methodology

Link equalization requires equalization for both TX and RX sides for the processor and

for the Endpoint device.

Adjusting transmitter and receiver of the lanes is done to improve signal reception

quality and for improving link robustness and electrical margin.

The link timing margins and voltage margins are strongly dependent on equalization of

the link.

The processor supports the following:

• Full TX Equalization: Three Taps Linear Equalization (Pre, Current and Post

cursors), with FS/LF (Full Swing /Low Frequency) values.

• Full RX Equalization and acquisition for AGC (Adaptive Gain Control), CDR (Clock

and Data Recovery), adaptive DFE (decision feedback equalizer) and adaptive

CTLE peaking (continuous time linear equalizer).

• Full adaptive phase 3 EQ compliant with PCI Express* Gen 3 and Gen 4

specification.

PCI Express* Hot Plug

PCI Express Hot Plug not supported.

7.1.4

7.1.5

Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors—PCIe* Interface

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

Datasheet, Volume 1 of 2 May 2025

146 Doc. No.: 743844, Rev.: 015

8.0 Direct Media Interface and On Package Interface

Direct Media Interface (DMI)

NOTE

The DMI interface is only present in 2-Chip platform processors.

Direct Media Interface (DMI) connects the processor and the PCH.

The main characteristics are as follows:

• 8 lanes Gen 4 DMI support

• 4 lanes Gen 4 Reduced DMI support

• 16 GT/s point-to-point DMI interface to PCH

• DC coupling - no capacitors between the processor and the PCH

• PCH end-to-end lane reversal across the link

• L0 (Active) and L1 (Low power) states support

• Half-Swing support (low-power/low-voltage)

DMI Error Flow

DMI can only generate SERR in response to errors; never SCI, SMI, MSI, PCI INT, or

GPE. Any DMI related SERR activity is associated with Device 0.

DMI Link Down

The DMI link going down is a fatal, unrecoverable error. If the DMI data link goes to

data link down, after the link was up, then the DMI link hangs the system by not

allowing the link to retrain to prevent data corruption. This link behavior is controlled

by the PCH.

Downstream transactions that had been successfully transmitted across the link prior

to the link going down may be processed as normal. No completions from

downstream, non-posted transactions are returned upstream over the DMI link after a

link down event.

On Package Interface (OPI)

OPI Support

The processor communicates with the PCIe using an internal interconnect BUS named

OPI.

8.1

8.1.1

8.1.2

8.2

8.2.1

Direct Media Interface and On Package Interface—Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400

Processors

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

May 2025 Datasheet, Volume 1 of 2

Doc. No.: 743844, Rev.: 015 147