743844-015.pdf - 第180页

Processor Clocking Signals Signal Name Description Dir. Buffer Type Link Type Availability BCLK_P BCLK_N 100 MHz Differential bus clock input to the processor . I Diff S/S Refresh/E/E Refresh -Processor Line P Processor …

MIPI CSI 2 Interface Signals

Signal Name Description Dir. Buffer Type Link Type Availability

CSI_A_DP[1:0]

CSI_A_DN[1:0]

CSI-2 Ports Data lane I DPHY Diff

P Processor Line

H/H Refresh

Processor Line

U/U Refresh

Processor Line

CSI_D_DP[1:0]

CSI_D_DN[1:0]

CSI-2 Ports Data lane I DPHY Diff

P Processor Line

H/H Refresh

Processor Line

U/U Refresh

Processor Line

CSI_B_DP[3:0]

CSI_B_DN[3:0]

CSI-2 Ports Data lane I DPHY Diff

P Processor Line

H/H Refresh

Processor Line

U/U Refresh

Processor Line

CSI_C_DP[3:0]

CSI_C_DN[3:0]

CSI-2 Ports Data lane I DPHY Diff

P Processor Line

H/H Refresh

Processor Line

U/U Refresh

Processor Line

CSI_A_CLK_P

CSI_A_CLK_N

CSI 2 Port A Clock

lane

I DPHY Diff

P Processor Line

H/H Refresh

Processor Line

U/U Refresh

Processor Line

CSI_B_CLK_P

CSI_B_CLK_N

CSI 2 Port A Clock

lane

I DPHY Diff

P Processor Line

H/H Refresh

Processor Line

U/U Refresh

Processor Line

CSI_C_CLK_P

CSI_C_CLK_N

CSI 2 Port A Clock

lane

I DPHY Diff

P Processor Line

H/H Refresh

Processor Line

U/U Refresh

Processor Line

CSI_D_CLK_P

CSI_D_CLK_N

CSI 2 Port A Clock

lane

I DPHY Diff

P Processor Line

H/H Refresh

Processor Line

U/U Refresh

Processor Line

CSI_RCOMP

CSI Resistance

Compensation

Analog DPHY SE

P Processor Line

H/H Refresh

Processor Line

U/U Refresh

Processor Line

12.7

Signal Description—Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

May 2025 Datasheet, Volume 1 of 2

Doc. No.: 743844, Rev.: 015 179

Processor Clocking Signals

Signal Name Description Dir.

Buffer

Type

Link

Type

Availability

BCLK_P

BCLK_N

100 MHz Differential bus clock input to

the processor.

I Diff

S/S Refresh/E/E

Refresh -Processor

Line

P Processor Line

H/H Refresh Processor

Line

U/U Refresh Processor

Line

CLK_NSSC_P

CLK_NSSC_N

38.4 MHz Differential bus clock input to

the processor.

I Diff

PCI_BCLKP

PCI_BCLKN

100 MHz Clock for PCI Express* logic

I Diff

Testability and Monitoring Signals

Signal Name Description Dir.

Buffer

Type

Link

Type

Availability

BPM#[3:0]

Breakpoint and Performance Monitor

Signals: Outputs from the processor that

indicate the status of breakpoints and

programmable counters used for monitoring

processor performance.

I/O GTL SE

S/S Refresh/HX/HX

Refresh/E/E Refresh

Processor Line

H/P Processor Line

U/U Refresh

Processor Line

PROC_PRDY#

Probe Mode Ready: PROC_PRDY# is a

processor output used by debug tools to

determine processor debug readiness.

O OD SE

S/S RefreshHX/HX

Refresh/E/E Refresh

Processor Line

H/P Processor Line

U/U Refresh

Processor Line

PROC_PREQ#

Probe Mode Request: PROC_PREQ# is used by

debug tools to request debug operation of the

processor.

I GTL SE

S/S RefreshHX/HX

Refresh/E/E Refresh

Processor Line

H/P Processor Line

U/U Refresh

Processor Line

PROC_TCK

Test Clock: This signal provides the clock input

for the processor Test Bus (also known as the

Test Access Port). This signal should be driven

low or allowed to float during power on Reset.

I GTL SE

S/S Refresh/E/E

Refresh Processor

Line

PROC_TDI

Test Data In: This signal transfers serial test

data into the processor. This signal provides the

serial input needed for JTAG specification

support.

I GTL SE

S/S Refresh

Processor Line

PROC_TDO

Test Data Out: This signal transfers serial test

data out of the processor. This signal provides

the serial output needed for JTAG specification

support.

O OD SE

S/S Refresh/E/E

Refresh Processor

Line

PROC_TMS

Test Mode Select: A JTAG specification support

signal used by debug tools.

I GTL SE

S/S Refresh/E/E

Refresh Processor

Line

PROC_JTAG_TCK

Test Clock: This signal provides the clock input

for the processor Test Bus (also known as the

Test Access Port). This signal should be driven

low or allowed to float during power on Reset.

I GTL SE

H/P/U/U Refresh

Processor Line

continued...

12.8

12.9

Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors—Signal Description

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

Datasheet, Volume 1 of 2 May 2025

180 Doc. No.: 743844, Rev.: 015

Signal Name Description Dir.

Buffer

Type

Link

Type

Availability

PROC_JTAG_TDI

Test Data In: This signal transfers serial test

data into the processor. This signal provides the

serial input needed for JTAG specification

support.

I GTL SE

H/P/U/U Refresh

Processor Line

PROC_JTAG_TDO

Test Data Out: This signal transfers serial test

data out of the processor. This signal provides

the serial output needed for JTAG specification

support.

O OD SE

H/P/U/U Refresh

Processor Line

PROC_JTAG_TMS

Test Mode Select: A JTAG specification support

signal used by debug tools.

I GTL SE

H/P/U/U Refresh

Processor Line

PROC_JTAG_TRST#

Test Reset: Resets the Test Access Port (TAP)

logic. This signal should be driven low during

power on Reset. Refer to the appropriate

processor Debug Port Design Guide for complete

implementation details.

I GTL SE

S/S Refresh/E/E

Refresh Processor

Line

H/P/U/U Refresh

Processor Line

DBG_PMODE Processor debug mode O GTL SE

H/P/U/U Refresh

Processor Line

Error and Thermal Protection Signals

Table 73. Error and Thermal Protection Signals

Signal Name Description Dir.

Buffer

Type

Link

Type

Availability

CATERR#

Catastrophic Error: This signal indicates that the

system has experienced a catastrophic error and

cannot continue to operate. The processor will set

this signal for non-recoverable machine check

errors or other unrecoverable internal errors.

CATERR# is used for signaling the following types

of errors: Legacy MCERRs, CATERR# is asserted for

16 BCLKs. Legacy IERRs, CATERR# remains

asserted until warm or cold reset.

O OD SE

S/S Refresh/E/E

Refresh Processor

Line

P Processor Line

U/U Refresh

Processor Line

PECI

Platform Environment Control Interface: A

serial sideband interface to the processor. It is used

primarily for thermal, power, and error

management. Details regarding the PECI electrical

specifications, protocols and functions can be found

in the RS-Platform Environment Control Interface

(PECI) Specification, Revision 3.0.

I/O

PECI,

Async

S/S Refresh/E/E

Refresh Processor

Line

P Processor Line

U/U Refresh

Processor Line

PROCHOT#

Processor Hot: PROCHOT# goes active when the

processor temperature monitoring sensor(s)

detects that the processor has reached its

maximum safe operating temperature. This

indicates that the processor Thermal Control Circuit

(TCC) has been activated, if enabled. This signal

can also be driven to the processor to activate the

TCC.

I/O

I:GTL/

O:OD

S/S Refresh/E/E

Refresh Processor

Line

P Processor Line

U/U Refresh

Processor Line

THERMTRIP#

Thermal Trip: The processor protects itself from

catastrophic overheating by use of an internal

thermal sensor. This sensor is set well above the

normal operating temperature to ensure that there

are no false trips. The processor will stop all

executions when the junction temperature exceeds

approximately 130 °C. This is signaled to the

system by the THRMTRIP# pin.

O OD SE

S/S Refresh/E/E

Refresh Processor

Line

P Processor Line

U/U Refresh

Processor Line

12.10

Signal Description—Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

May 2025 Datasheet, Volume 1 of 2

Doc. No.: 743844, Rev.: 015 181