743844-015.pdf - 第66页

While individual threads can request low-power C -states, power saving actions only take place once the processor IA core C -state is resolved. processor IA core C -states are automatically resolved by the processor . Fo…

OS/HW Controlled P-states

Enhanced Intel SpeedStep

Technology

Enhanced Intel SpeedStep

Technology enables OS to control and select P-state. For

more information, refer to Enhanced Intel SpeedStep

Technology on page 49.

Intel

Speed Shift Technology

Intel

Speed Shift Technology is an energy efficient method of frequency control by

the hardware rather than relying on OS control. For more details, refer to Intel

Speed Shift Technology on page 50.

Low-Power Idle States

When the processor is idle, low-power idle states (C-states) are used to save power.

More power savings actions are taken for numerically higher C-states. However,

deeper C-states have longer exit and entry latencies. Resolution of C-states occurs at

the thread, processor IA core, and processor package level.

CAUTION

Long-term reliability cannot be assured unless all the Low-Power Idle States are

enabled.

Figure 15. Idle Power Management Breakdown of the Processor IA Cores

Thread 0 Thread 1

Core 0 State

Thread 0 Thread 1

Core N State

Processor Package State

3.2.1

3.2.1.1

3.2.1.2

3.2.2

Power Management—Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

May 2025 Datasheet, Volume 1 of 2

Doc. No.: 743844, Rev.: 015 65

While individual threads can request low-power C-states, power saving actions only

take place once the processor IA core C-state is resolved. processor IA core C-states

are automatically resolved by the processor. For thread and processor IA core C-

states, a transition to and from C0 state is required before entering any other C-state.

Requesting the Low-Power Idle States

The primary software interfaces for requesting low-power idle states are through the

MWAIT instruction with sub-state hints and the HLT instruction (for C1 and C1E).

However, the software may make C-state requests using the legacy method of I/O

reads from the ACPI-defined processor clock control registers, referred to as P_LVLx.

This method of requesting C-states provides legacy support for operating systems that

initiate C-state transitions using I/O reads.

For legacy operating systems, P_LVLx I/O reads are converted within the processor to

the equivalent MWAIT C-state request. Therefore, P_LVLx reads do not directly result

in I/O reads to the system. The feature, known as I/O MWAIT redirection, should be

enabled in the BIOS..

The BIOS can write to the C-state range field of the PMG_IO_CAPTURE MSR to restrict

the range of I/O addresses that are trapped and emulate MWAIT like functionality. Any

P_LVLx reads outside of this range do not cause an I/O redirection to MWAIT(Cx) like

the request. They fall through like a normal I/O instruction.

When P_LVLx I/O instructions are used, MWAIT sub-states cannot be defined. The

MWAIT sub-state is always zero if I/O MWAIT redirection is used. By default, P_LVLx

I/O redirections enable the MWAIT 'break on EFLAGS.IF’ feature that triggers a wake

up on an interrupt, even if interrupts are masked by EFLAGS.IF.

Processor IA Core C-State Rules

The following are general rules for all processor IA core C-states unless specified

otherwise:

• A processor IA core C-State is determined by the lowest numerical thread state

(such as Thread 0 requests C1E while Thread 1 requests C6 state, resulting in a

processor IA core C1E state). Refer to G, S, and C Interface State Combinations

table.

• A processor IA core transitions to C0 state when:

— An interrupt occurs

— There is an access to the monitored address if the state was entered using an

MWAIT/Timed MWAIT instruction

— The deadline corresponding to the Timed MWAIT instruction expires

• An interrupt directed toward a single thread wakes up only that thread.

• If any thread in a processor IA core is active (in C0 state), the core’s C-state will

resolve to C0.

• Any interrupt coming into the processor package may wake any processor IA core.

• A system reset re-initializes all processor IA cores.

3.2.3

3.2.4

Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors—Power Management

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

Datasheet, Volume 1 of 2 May 2025

66 Doc. No.: 743844, Rev.: 015

Table 7. Core C-states

Core C-

State

C-State Request

Instruction

Description

C0 N/A

The normal operating state of a processor IA core where a code is being

executed

C1 MWAIT(C1)

AutoHalt - core execution stopped, autonomous clock gating (package in

C0 state)

C1E MWAIT(C1E)

Core C1 + lowest frequency and voltage operating point (package in C0

state)

C6-C10

MWAIT(C6/C8/10)

or IO

read=P_LVL3//6/8

Processor IA, flush their L1 instruction cache, the L1 data cache, and L2

cache to the LLC shared cache cores save their architectural state to an

SRAM before reducing IA cores voltage, if possible may also be reduced to

0V. Core clocks are off.

Core C-State Auto-Demotion

In general, deeper C-states, such as C6, have long latencies and have higher energy

entry/exit costs. The resulting performance and energy penalties become significant

when the entry/exit frequency of a deeper C-state is high. Therefore, incorrect or

inefficient usage of deeper C-states have a negative impact on battery life and idle

power. To increase residency and improve battery life and idle power in deeper C-

states, the processor supports C-state auto-demotion.

C-State auto-demotion:

• C6 to C1/C1E

The decision to demote a processor IA core from C6 to C1/C1E is based on each

processor IA core’s immediate residency history. Upon each processor IA core C6

request, the processor IA core C-state is demoted to C1 until a sufficient amount of

residency has been established. At that point, a processor IA core is allowed to go into

C6 . If the interrupt rate experienced on a processor IA core is high and the processor

IA core is rarely in a deep C-state between such interrupts, the processor IA core can

be demoted to a C1 state.

This feature is disabled by default. BIOS should enable it in the

PMG_CST_CONFIG_CONTROL register. The auto-demotion policy is also configured by

this register.

Package C-States

The processor supports C0, C2, C3, C6, C8, and C10 package states. The following is a

summary of the general rules for package C-state entry. These apply to all package C-

states, unless specified otherwise:

• A package C-state request is determined by the lowest numerical processor IA

core C-state amongst all processor IA cores.

• A package C-state is automatically resolved by the processor depending on the

processor IA core idle power states and the status of the platform components.

— Each processor IA core can be at a lower idle power state than the package if

the platform does not grant the processor permission to enter a requested

package C-state.

— The platform may allow additional power savings to be realized in the

processor.

3.2.5

Power Management—Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

May 2025 Datasheet, Volume 1 of 2

Doc. No.: 743844, Rev.: 015 67