743844-015.pdf - 第47页

NOTES 1. L1 Data cache (DCU) - 48KB (P-core) - 32KB (E-Core) 2. L1 Instruction cache (IFU) - 32KB (P-Core) - 64KB (E-Core) 3. MLC - Mid Level Cache - 2MB (P-Core) - 4MB (shared by 4 E-Cores ) Ring Interconnect The Ring i…

• For E Cores The 2nd level cache is shared between 4 physical cores.

• The size of the LLC is SKU specific with a maximum of 3MB per P physical core or

4 E cores and is a 12-way associative cache.

IA Cores Level 1 and Level 2 Caches

P Cores 1st level cache is divided into a data cache (DFU) and an instruction cache

(IFU). The processor 1st level cache size is 48KB for data and 32KB for instructions.

The 1st level cache is an 12-way associative cache.

E Cores 1st level cache is divided into a data cache (DFU) and an instruction cache

(IFU). The processor 1st level cache size is 32KB for data and 64KB for instructions.

The 1st level cache is an 8-way associative cache.

The 2nd level cache holds both data and instructions. It is also referred to as mid-level

cache or MLC.

For P/H/H Refresh/U, S/HX 8P+8E, S 6P+0E predecessor lines, the P Cores 2nd level

cache size is 1.25 MB and is a 10-way non-inclusive associative cache, 4 E Cores

processors 2nd level cache size is 2MB and is a 16-way non-inclusive associative

cache.

For S refresh 8P+8E, S refresh 6P+0E predecessor lines, the P Cores 2nd level cache

size is 1.25 MB and is a 10-way non-inclusive associative cache, 4 E Cores processors

2nd level cache size is 2MB and is a 16-way non-inclusive associative cache.

For S/HX 8P+16E and E Processors Lines, the P Cores 2nd level cache size is2 MB and

is a 16-way non-inclusive associative cache, 4 E Cores processors 2nd level cache size

is 4MB and is a 16-way non-inclusive associative cache.

For S Refresh/HX Refresh 8P+16E Processors Lines, the P Cores 2nd level cache size is

2 MB and is a 16-way non-inclusive associative cache, 4 E Cores processors 2nd level

cache size is 4MB and is a 16-way non-inclusive associative cache

Figure 11. Hybrid Cache

2.4.2

Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors—Technologies

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

Datasheet, Volume 1 of 2 May 2025

46 Doc. No.: 743844, Rev.: 015

NOTES

1. L1 Data cache (DCU) - 48KB (P-core) - 32KB (E-Core)

2. L1 Instruction cache (IFU) - 32KB (P-Core) - 64KB (E-Core)

3. MLC - Mid Level Cache - 2MB (P-Core) - 4MB (shared by 4 E-Cores)

Ring Interconnect

The Ring is a high speed, wide interconnect that links the processor cores, processor

graphics and the System Agent.

The Ring shares frequency and voltage with the Last Level Cache (LLC).

The Ring's frequency dynamically changes. Its frequency is relative to both processor

cores and processor graphics frequencies.

Intel

Performance Hybrid Architecture

The processor contains two types of cores, denoted as P-Cores and E-Cores (P core is

a Performance core and E core is efficient core ).

The P-Cores and E-Cores share the same instruction set.

The available instruction sets, when hybrid computing is enabled, is limited compared

to the instruction sets available to P-Cores.

P core and E core frequency's will be determined by the processor algorithmic, to

maximize performance and power optimization.

For more details, refer to: https://www.intel.com/content/www/us/en/developer/

articles/technical/hybrid-architecture.html

NOTE

Hybrid Computing may not be available on all SKUs.

Intel

Turbo Boost Max Technology 3.0

The Intel

Turbo Boost Max Technology 3.0 (ITBMT 3.0) grants a different maximum

Turbo frequency for individual processor cores.

To enable ITBMT 3.0 the processor exposes individual core capabilities; including

diverse maximum turbo frequencies.

An operating system that allows for varied per core frequency capability can then

maximize power savings and performance usage by assigning tasks to the faster

cores, especially on low core count workloads.

Processors enabled with these capabilities can also allow software (most commonly a

driver) to override the maximum per-core Turbo frequency limit and notify the

operating system via an interrupt mechanism.

2.4.3

2.4.4

2.4.5

Technologies—Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

May 2025 Datasheet, Volume 1 of 2

Doc. No.: 743844, Rev.: 015 47

For more information on the Intel

Turbo Boost Max 3.0 Technology, refer to http://

www.intel.com/content/www/us/en/architecture-and-technology/turbo-boost/turbo-

boost-max-technology.html

NOTE

Intel

Turbo Boost Max 3.0 Technology may not be available on all SKUs.

Power Aware Interrupt Routing (PAIR)

The processor includes enhanced power-performance technology that routes interrupts

to threads or processor IA cores based on their sleep states. As an example, for

energy savings, it routes the interrupt to the active processor IA cores without waking

the deep idle processor IA cores. For performance, it routes the interrupt to the idle

(C1) processor IA cores without interrupting the already heavily loaded processor IA

cores. This enhancement is most beneficial for high-interrupt scenarios like Gigabit

LAN, WLAN peripherals, etc.

Intel

Hyper-Threading Technology

The processor supports Intel

Hyper-Threading Technology (Intel

HT Technology)

that allows an execution processor IA core to function as two logical processors. While

some execution resources such as caches, execution units, and buses are shared,

each logical processor has its own architectural state with its own set of general-

purpose registers and control registers. This feature should be enabled using the BIOS

and requires operating system support.

Intel recommends enabling Intel

Hyper-Threading Technology with Microsoft*

Windows* 7 or newer and disabling Intel

Hyper-Threading Technology using the

BIOS for all previous versions of Windows* operating systems.

NOTE

Intel

HT Technology may not be available on all SKUs.

Intel

Turbo Boost Technology 2.0

The Intel

Turbo Boost Technology 2.0 allows the processor IA core/processor

graphics core to opportunistically and automatically run faster than the processor IA

core base frequency/processor graphics base frequency if it is operating below power,

temperature, and current limits. The Intel

Turbo Boost Technology 2.0 feature is

designed to increase the performance of both multi-threaded and single-threaded

workloads.

Compared with previous generation products, Intel

Turbo Boost Technology 2.0 will

increase the ratio of application power towards Processor Base Power (a.k.a TDP) and

also allows to increase power above Processor Base Power (a.k.a TDP) as high as PL2

for short periods of time. Thus, thermal solutions and platform cooling that are

designed to less than thermal design guidance might experience thermal and

performance issues since more applications will tend to run at the maximum power

limit for significant periods of time.

2.4.6

2.4.7

2.4.8

Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors—Technologies

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

Datasheet, Volume 1 of 2 May 2025

48 Doc. No.: 743844, Rev.: 015