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Perform Carry-Less Multiplication Quad Word Instruction The processor supports the carry-less multiplication instruction, ie, P erform Carry -Less Multiplication Quad W ord Instruction (PCLMULQDQ). PCLMULQDQ is a Single …

• Enable SMM code execution range checking

• Select whether SMM Save State is to be written to legacy SMRAM or to MSRs

• Determine if a thread is going to be delayed entering SMM

• Determine if a thread is blocked from entering SMM

• Targeted SMI, enable/disable threads from responding to SMIs, both VLWs, and

IPI

For the above features, BIOS should test the associated capability bit before

attempting to access any of the above registers. The capability bits are discussed in

the register description.

For more information, refer to the Intel

Trusted Execution Technology Measured

Launched Environment Programming Guide at:

http://www.intel.com/content/www/us/en/software-developers/intel-txt-software-

development-guide.html.

NOTE

Intel

TXT Technology may not be available on all SKUs.

Intel

Advanced Encryption Standard New Instructions

The processor supports Intel

Advanced Encryption Standard New Instructions (Intel

AES-NI) that are a set of Single Instruction Multiple Data (SIMD) instructions that

enable fast and secure data encryption and decryption based on the Advanced

Encryption Standard (AES). Intel

AES-NI is valuable for a wide range of

cryptographic applications, such as applications that perform bulk encryption/

decryption, authentication, random number generation, and authenticated encryption.

AES is broadly accepted as the standard for both government and industrial

applications and is widely deployed in various protocols.

Intel

AES-NI consists of six Intel

SSE instructions. Four instructions, AESENC,

AESENCLAST, AESDEC, and AESDELAST facilitate high-performance AES encryption

and decryption. The other two, AESIMC and AESKEYGENASSIST, support the AES key

expansion procedure. Together, these instructions provide full hardware for supporting

AES; offering security, high performance, and a great deal of flexibility.

This generation of the processor has increased the performance of the Intel

AES-NI

significantly compared to previous products.

The Intel

AES-NI specifications and functional descriptions are included in the Intel

64 Architectures Software Developer’s Manual, Volume 2. Available at:

http://www.intel.com/products/processor/manuals

NOTE

Intel

AES-NI Technology may not be available on all SKUs.

2.3.2

Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors—Technologies

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

Datasheet, Volume 1 of 2 May 2025

40 Doc. No.: 743844, Rev.: 015

Perform Carry-Less Multiplication Quad Word Instruction

The processor supports the carry-less multiplication instruction, ie, Perform Carry-Less

Multiplication Quad Word Instruction (PCLMULQDQ). PCLMULQDQ is a Single

Instruction Multiple Data (SIMD) instruction that computes the 128-bit carry-less

multiplication of two 64-bit operands without generating and propagating carries.

Carry-less multiplication is an essential processing component of several cryptographic

systems and standards. Hence, accelerating carry-less multiplication can significantly

contribute to achieving high-speed secure computing and communication.

PCLMULQDQ specifications and functional descriptions are included in the Intel

Architectures Software Developer’s Manual, Volume 2. Available at:

http://www.intel.com/products/processor/manuals

Intel

Secure Key

The processor supports Intel

Secure Key (formerly known as Digital Random Number

Generator or DRNG), a software visible random number generation mechanism

supported by a high-quality entropy source. This capability is available to

programmers through the RDRAND instruction. The resultant random number

generation capability is designed to comply with existing industry standards in this

regard (ANSI X9.82 and NIST SP 800-90).

Some possible usages of the RDRAND instruction include cryptographic key generation

as used in a variety of applications, including communication, digital signatures,

secure storage, etc.

RDRAND specifications and functional descriptions are included in the Intel

Architectures Software Developer’s Manual, Volume 2. Available at:

http://www.intel.com/products/processor/manuals

Execute Disable Bit

The Execute Disable Bit allows memory to be marked as non-executable when

combined with a supporting operating system. If code attempts to run in non-

executable memory, the processor raises an error to the operating system. This

feature can prevent some classes of viruses or worms that exploit buffer overrun

vulnerabilities and can, thus, help improve the overall security of the system.

Boot Guard Technology

Boot Guard technology is a part of boot integrity protection technology. Boot Guard

can help protect the platform boot integrity by preventing the execution of

unauthorized boot blocks. With Boot Guard, platform manufacturers can create boot

policies such that invocation of an unauthorized (or untrusted) boot block will trigger

the platform protection per the manufacturer's defined policy.

With verification based in the hardware, Boot Guard extends the trust boundary of the

platform boot process down to the hardware level.

Boot Guard accomplishes this by:

• Providing of hardware-based Static Root of Trust for Measurement (S-RTM) and

the Root of Trust for Verification (RTV) using Intel architectural components.

2.3.3

2.3.4

2.3.5

2.3.6

Technologies—Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

May 2025 Datasheet, Volume 1 of 2

Doc. No.: 743844, Rev.: 015 41

• Providing of architectural definition for platform manufacturer Boot Policy.

• Enforcing manufacturer provided Boot Policy using Intel architectural components.

Benefits of this protection are that Boot Guard can help maintain platform integrity by

preventing re-purposing of the manufacturer’s hardware to run an unauthorized

software stack.

NOTE

Boot Guard availability may vary between the different SKUs.

Intel

Supervisor Mode Execution Protection

Intel

Supervisor Mode Execution Protection (Intel

SMEP) is a mechanism that

provides the next level of system protection by blocking malicious software attacks

from user mode code when the system is running in the highest privilege level. This

technology helps to protect from virus attacks and unwanted code from harming the

system. For more information, refer to Intel

64 Architectures Software Developer’s

Manual, Volume 3 at:

http://www.intel.com/products/processor/manuals

Intel

Supervisor Mode Access Protection

Intel

Supervisor Mode Access Protection (Intel

SMAP) is a mechanism that provides

next level of system protection by blocking a malicious user from tricking the

operating system into branching off user data. This technology shuts down very

popular attack vectors against operating systems.

For more information, refer to the Intel

64 Architectures Software Developer’s

Manual, Volume 3:

http://www.intel.com/products/processor/manuals

Intel

Secure Hash Algorithm Extensions

The Intel

Secure Hash Algorithm Extensions (Intel

SHA Extensions) is one of the

most commonly employed cryptographic algorithms. Primary usages of SHA include

data integrity, message authentication, digital signatures, and data de-duplication. As

the pervasive use of security solutions continues to grow, SHA can be seen in more

applications now than ever. The Intel

SHA Extensions are designed to improve the

performance of these compute-intensive algorithms on Intel

architecture-based

processors.

The Intel

SHA Extensions are a family of seven instructions based on the Intel

Streaming SIMD Extensions (Intel

SSE) that are used together to accelerate the

performance of processing SHA-1 and SHA-256 on Intel architecture-based

processors. Given the growing importance of SHA in our everyday computing devices,

the new instructions are designed to provide a needed boost of performance to

hashing a single buffer of data. The performance benefits will not only help improve

responsiveness and lower power consumption for a given application, but they may

also enable developers to adopt SHA in new applications to protect data while

delivering to their user experience goals. The instructions are defined in a way that

simplifies their mapping into the algorithm processing flow of most software libraries,

thus enabling easier development.

2.3.7

2.3.8

2.3.9

Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors—Technologies

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

Datasheet, Volume 1 of 2 May 2025

42 Doc. No.: 743844, Rev.: 015