743844-015.pdf - 第87页

On-Demand Mode The processor provides an auxiliary mechanism that allows system software to force the processor to reduce its power consumption using clock modulation. This mechanism is referred to as “On-Demand” mode an…

thermal design should allow the power delivery circuitry to operate within its

temperature specification even while the processor is operating at its Processor Base

Power.

NOTE

During PROCHOT demotion, the core frequency may be reduced below LFM for several

uSec.

Thermal Solution Design and PROCHOT# Behavior

With a properly designed and characterized thermal solution, it is anticipated that

PROCHOT# will only be asserted for very short periods of time when running the most

power intensive applications. The processor performance impact due to these brief

periods of TCC activation is expected to be so minor that it would be immeasurable.

However, an under-designed thermal solution that is not able to prevent excessive

assertion of PROCHOT# in the anticipated ambient environment may:

• Cause a noticeable performance loss.

• Result in prolonged operation at or above the specified maximum junction

temperature and affect the long-term reliability of the processor.

• May be incapable of cooling the processor even when the TCC is active

continuously (in extreme situations).

Low-Power States and PROCHOT# Behavior

Depending on package power levels during package C-states, outbound PROCHOT#

may de-assert while the processor is idle as power is removed from the signal. Upon

wake up, if the processor is still hot, the PROCHOT# will re-assert, although typically

package idle state residency should resolve any thermal issues. The PECI interface is

fully operational during all C-states and it is expected that the platform continues to

manage processor IA core and package thermals even during idle states by regularly

polling for thermal data over PECI.

THRMTRIP# Signal

Regardless of enabling the automatic or on-demand modes, in the event of a

catastrophic cooling failure, the package will automatically shut down when the silicon

has reached an elevated temperature that risks physical damage to the product. At

this point, the THRMTRIP# signal will go active.

Critical Temperature Detection

Critical Temperature detection is performed by monitoring the package temperature.

This feature is intended for graceful shutdown before the THRMTRIP# is activated.

However, the processor execution is not guaranteed between critical temperature and

THRMTRIP#. If the Adaptive Thermal Monitor is triggered and the temperature

remains high, a critical temperature status and sticky bit are latched in the

PACKAGE_THERM_STATUS (0x1B1) MSR and the condition also generates a thermal

interrupt, if enabled.

4.1.3.8

4.1.3.9

4.1.3.10

4.1.3.11

Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors—Thermal Management

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

Datasheet, Volume 1 of 2 May 2025

86 Doc. No.: 743844, Rev.: 015

On-Demand Mode

The processor provides an auxiliary mechanism that allows system software to force

the processor to reduce its power consumption using clock modulation. This

mechanism is referred to as “On-Demand” mode and is distinct from Adaptive Thermal

Monitor and bi-directional PROCHOT#. The processor platforms should not rely on

software usage of this mechanism to limit the processor temperature. On-Demand

Mode can be accomplished using processor MSR or chipset I/O emulation. On-Demand

Mode may be used in conjunction with the Adaptive Thermal Monitor. However, if the

system software tries to enable On-Demand mode at the same time the TCC is

engaged, the factory configured the duty cycle of the TCC will override the duty cycle

selected by the On-Demand mode. If the I/O based and MSR-based On-Demand

modes are in conflict, the duty cycle selected by the I/O emulation-based On-Demand

mode will take precedence over the MSR-based On-Demand Mode.

MSR Based On-Demand Mode

If Bit 4 of the IA32_CLOCK_MODULATION MSR is set to 1, the processor will

immediately reduce its power consumption using modulation of the internal processor

IA core clock, independent of the processor temperature. The duty cycle of the clock

modulation is programmable using bits [3:1] of the same IA32_CLOCK_MODULATION

MSR. In this mode, the duty cycle can be programmed in either 12.5% or 6.25%

increments (discoverable using CPUID). Thermal throttling using this method will

modulate each processor IA core's clock independently.

I/O Emulation-Based On-Demand Mode

I/O emulation-based clock modulation provides legacy support for operating system

software that initiates clock modulation through I/O writes to ACPI defined processor

clock control registers on the chipset (PROC_CNT). Thermal throttling using this

method will modulate all processor IA cores simultaneously.

Intel

Memory Thermal Management

DRAM Thermal Aggregation

P-Unit firmware is responsible for aggregating DRAM temperature sources into a per-

DIMM reading as well as an aggregated virtual 'max' sensor reading. At reset, MRC

communicates to the MC the valid channels and ranks as well as DRAM type. At that

time, Punit firmware sets up a valid channel and rank mask that is then used in the

thermal aggregation algorithm to produce a single maximum temperature

DRAM Thermal Monitoring

• DRAM thermal sensing Periodic DDR thermal reads from DDR

• DRAM thermal calculation Punit reads of DDR thermal information direct from the

memory controller (MR4 or MPR) Punit estimation of a virtual maximum DRAM

temperature based on per-rank readings. Application of thermal filter to the virtual

maximum temperature.

4.1.3.12

4.1.3.13

4.1.3.14

4.1.4

Thermal Management—Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

May 2025 Datasheet, Volume 1 of 2

Doc. No.: 743844, Rev.: 015 87

DRAM Refresh Rate Control

The MRC will natively interface with MR4 or MPR readings to adjust DRAM refresh rate

as needed to maintain data integrity. This capability is enabled by default and occurs

automatically. Direct override of this capability is available for debug purposes, but

this cannot be adjusted during runtime.

General Notes

The following notes apply to Processor Line Power and Frequency Specifications on

page 89 and Processor Line Thermal and Power Specifications on page 101.

Note Definition

The Processor Base Power (a.k.a TDP) and Assured Power (cTDP) values are the average power

dissipation in junction temperature operating condition limit, for the SKU Segment and

Configuration, for which the processor is validated during manufacturing when executing an

associated Intel-specified high-complexity workload at the processor IA core frequency

corresponding to the configuration and SKU.

Thermal workload (Processor Base Power (a.k.a TDP) ) may consist of a combination of processor

IA core intensive and graphics core intensive applications.

3 Can be modified at runtime by MSR writes, with MMIO and with PECI commands.

'Turbo Time Parameter' is a mathematical parameter (units of seconds) that controls the processor

turbo algorithm using a moving average of energy usage. Do not set the Turbo Time Parameter to a

value less than 0.1 seconds. refer to Platform Power Control on page 78 for further information.

The shown limit is a time averaged-power, based upon the Turbo Time Parameter. Absolute product

power may exceed the set limits for short durations or under virus or uncharacterized workloads.

The Processor will be controlled to a specified power limit as described in

Intel

Turbo Boost

Technology 2.0 Power Monitoring on page 49. If the power value and/or 'Turbo Time Parameter' is

changed during runtime, it may take a short period of time (approximately 3 to 5 times the 'Turbo

Time Parameter') for the algorithm to settle at the new control limits.

7 This is a hardware default setting and not a behavioral characteristic of the part.

8 For controllable turbo workloads, the PL2 limit may be exceeded for up to 10ms.

Power limits may vary depending on if the product supports the Minimum Assured Power (cTDP

Down) and/or Maximum Assured Power (cTDP Up) modes. Default power limits can be found in the

PKG_PWR_SKU MSR (614h).

The processor die do not reach maximum sustained power simultaneously since the sum of the 2

die's estimated power budget is controlled to be equal to or less than the package Processor Base

Power (a.k.a TDP) (PL1) limit.

Minimum Assured Power(cTDP Down) power is based on 96EU equivalent graphics configuration.

Minimum Assured Power(cTDP Down) does not decrease the number of active Processor Graphics

EUs but relies on Power Budget Management (PL1) to achieve the specified power level.

12 May vary based on SKU.

• The formula of PL2=PL1*1.25 is the hardware.

• PL2- SoC opportunistic higher Average Power with limited duration controlled by Tau_PL1

setting,

• the larger the Tau, the longer the PL2 duration.

• PL1 Tau - PL1 average power is controlled via PID algorithm with this Tau, The larger the Tau,

the longer the PL2 duration.

continued...

4.2

Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors—Thermal Management

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

Datasheet, Volume 1 of 2 May 2025

88 Doc. No.: 743844, Rev.: 015