743844-015.pdf - 第219页
15.0 CPU And Device IDs CPUID Table 101. CPUID Format SKU Stepping CPUID Reserved [31:28] Extended Family [27:20] Extended Model [19:16] Reserved [15:14] Processo r Type [13:12] Family Code [11:8] Model Number [7:4] Step…
Package Parameter PX Processor Line
Die Side Capacitors No
Die Configuration 2 Dice Multi Chip Package (MCP)
Package Dimensions
Nominal Package Size 25 X 40 mm
Z
Substrate Z= 0.594+/-0.08 mm
1.171±0.082 (Bottom of BGA to Top of
Die)
Minimum Ball/Pin pitch 0.62 mm BP
Package Storage Specifications
Parameter Description Minimum Maximum
T
ABSOLUTE STORAGE
The non-operating device storage temperature.
Damage (latent or otherwise) may occur when
subjected to this temperature for any length of
time in Intel Original sealed moisture barrier bag
and / or box.
-25°C 125°C
T
SUSTAINED STORAGE
The ambient storage temperature limit (in
shipping media) for the sustained period of time
-5°C 40°C
RH
SUSTAINED STORAGE
The maximum device storage relative humidity for
the sustained period of time as specified below in
Intel Original sealed moisture barrier bag and / or
box
60%@ 24°C
TIME
SUSTAINED STORAGE
Maximum time: associated with customer shelf life
in Intel Original sealed moisture barrier bag and /
or box
NA
Moisture Sensitive
Devices: 60 months
from bag seal date; Non-
moisture sensitive
devices: 60 months from
lot date
Storage Conditions
Processors in a non-operational state may be installed in a platform, in a tray, boxed, or loose
and may be sealed in airtight package or exposed to free air. Under these conditions,
processor landings should not be connected to any supply voltages, have any I/Os biased, or
receive any clocks. Upon exposure to "free air" (that is, unsealed packaging or a device
removed from packaging material), the processor should be handled in accordance with
moisture sensitivity labeling (MSL) as indicated on the packaging material. Boxed Land Grid
Array packaged (LGA) processors are MSL 1 ('unlimited' or unaffected) as they are not heated
in order to be inserted in the socket.
Notes: 1. T
ABSOLUTE STORAGE
applies to the un-assembled component only and does not apply to the shipping media,
moisture barrier bags or desiccant. Refers to a component device that is not assembled in a board or socket
that is not to be electrically connected to a voltage reference or I/O signals.
2. Specified temperatures are based on data collected. Exceptions for surface mount re-flow are specified by
applicable JEDEC J-STD-020 documents. The JEDEC, J-STD-020 moisture level rating and associated handling
practices apply to all moisture sensitive devices removed from the moisture barrier bag.
3. Post board attaches storage temperature limits are not specified for non-Intel branded boards. Consult your
board manufacturer for storage specifications.
14.2
R
Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors—Package Mechanical Specifications
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
Datasheet, Volume 1 of 2 May 2025
218 Doc. No.: 743844, Rev.: 015
15.0 CPU And Device IDs
CPUID
Table 101. CPUID Format
SKU Stepping CPUID Reserved
[31:28]
Extended
Family
[27:20]
Extended
Model
[19:16]
Reserved
[15:14]
Processo
r Type
[13:12]
Family
Code
[11:8]
Model
Number
[7:4]
Stepping
ID [3:0]
S/S
Refresh
8P+16E
B-0 0xB0671 Reserved 0000000b 1011b Reserved 00b 0110b 0111b 0001b
S/S
Refresh
8P+8E
C-0 0xB06F2 Reserved 0000000b 1011b Reserved 00b 0110b 1111b 0010b
S/S
Refresh
6P+0E
H-0 0xB06F5 Reserved 0000000b 1011b Reserved 00b 0110b 1111b 0101b
HX/HX
Refresh
8P+16E
B-0 0xB0671 Reserved 0000000b 1011b Reserved 00b 0110b 0111b 0001b
HX 8P
+8E
C-0 0xB06F2 Reserved 0000000b 1011b Reserved 00b 0110b 1111b 0010b
H 6P+8E J-0 0xB06A2 Reserved 0000000b 1011b Reserved 00b 0110b 1010b 0010b
H
Refresh
6P+8E
J-0 0xB06A2 Reserved 0000000b 1011b Reserved 00b 0110b 1010b 0010b
P 6P+8E J-0 0xB06A2 Reserved 0000000b 1011b Reserved 00b 0110b 1010b 0010b
PX 6E
+8P
J-0 0xB06A2 Reserved 0000000b 1011b Reserved 00b 0110b 1010b 0010b
U/U
Refresh
2E+8P
Q-0 0xB06A3 Reserved 0000000b 1011b Reserved 00b 0110b 1010b 0011b
E/E
Refresh
8P+0E
B-0 0xB0671 Reserved 0000000b 1011b Reserved 00b 0110b 0111b 0001b
15.1
R
CPU And Device IDs—Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
May 2025 Datasheet, Volume 1 of 2
Doc. No.: 743844, Rev.: 015 219
NOTES
• The Extended Family, Bits [27:20] are used in conjunction with the Family Code,
specified in Bits[11:8], to indicate whether the processor belongs to Intel
®
Core
™
processor family.
• The Extended Model, Bits [19:16] in conjunction with the Model Number, specified
in Bits [7:4], are used to identify the model of the processor within the processor's
family.
• The Family Code corresponds to Bits [11:8] of the EDX register after RESET, Bits
[11:8] of the EAX register after the CPUID instruction is executed with a 1 in the
EAX register, and the generation field of the Device ID register accessible through
Boundary Scan.
• The Model Number corresponds to Bits [7:4] of the EDX register after RESET, Bits
[7:4] of the EAX register after the CPUID instruction is executed with a 1 in the
EAX register, and the model field of the Device ID register accessible through
Boundary Scan.
• The Stepping ID in Bits [3:0] indicates the revision number of that model.
• When EAX is initialized to a value of '1', the CPUID instruction returns the
Extended Family, Extended Model, Processor Type, Family Code, Model Number
and Stepping ID value in the EAX register. Note that the EDX processor signature
value after reset is equivalent to the processor signature output value in the EAX
register.
Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX and EDX
registers after the CPUID instruction is executed with a 2 in the EAX register.
PCI Configuration Header
Every PCI-compatible function has a standard PCI configuration header, as shown in
the table below. This includes mandatory registers (Bold) to determine which driver to
load for the device. Some of these registers define ID values for the PCI function,
which are described in this chapter.
Table 102. PCI Configuration Header
Byte3 Byte2 Byte1 Byte0 Address
Device ID Vendor ID (0x8086) 00h
Status Command 04h
Class Code Revision ID 08h
BIST Header Type Latency Timer Cache Line Size 0Ch
Base Address Register0 (BAR0) 10h
Base Address Register1 (BAR1) 14h
Base Address Register2 (BAR2) 18h
Base Address Register3 (BAR3) 1Ch
Base Address Register4 (BAR4) 20h
Base Address Register5 (BAR5) 24h
continued...
15.2
R
Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors—CPU And Device IDs
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
Datasheet, Volume 1 of 2 May 2025
220 Doc. No.: 743844, Rev.: 015