743844-015.pdf - 第131页

Conditional Self-Refresh During S0 idle state, system memory may be conditionally placed into self -refresh state when the processor is in package C3 or deeper power state. Refer to Intel ® Rapid Memory P ower Management…

• Active Power-down (APD): This mode is entered if there are open pages when

de-asserting CKE. In this mode the open pages are retained. Power-saving in this

mode is the lowest. Power consumption of DDR is defined by IDD3P. Exiting this

mode is fined by tXP – a small number of cycles.

• Pre-charged Power-down (PPD): This mode is entered if all banks in DDR are

pre-charged when de-asserting CKE. Power-saving in this mode is intermediate –

better than APD. Power consumption is defined by IDD2P. Exiting this mode is

defined by tXP. The difference from APD mode is that when waking-up, all page-

buffers are empty.)

*APD is default in P and U Processor line, otherwise it's "No Power down".

The CKE is determined per rank, whenever it is inactive. Each rank has an idle

counter. The idle-counter starts counting as soon as the rank has no accesses, and if it

expires, the rank may enter power-down while no new transactions to the rank arrive

to queues. The idle-counter begins counting at the last incoming transaction arrival. It

is important to understand that since the power-down decision is per rank, the IMC

can find many opportunities to power down ranks, even while running memory

intensive applications; the savings are significant (may be few Watts, according to

DDR specification). This is significant when each channel is populated with more

ranks.

Selection of power modes should be according to power-performance or a thermal

trade-off of a given system:

• When trying to achieve maximum performance and power or thermal

consideration is not an issue: use no power-down

• In a system which tries to minimize power-consumption, try using the deepest

power-down mode possible

• In high-performance systems with dense packaging (that is, tricky thermal

design) the power-down mode should be considered in order to reduce the heating

and avoid DDR throttling caused by the heating.

The idle timer expiration count defines the # of DCLKs that a rank is idle that causes

entry to the selected power mode. As this timer is set to a shorter time the IMC will

have more opportunities to put the DDR in power-down. There is no BIOS hook to set

this register. Customers choosing to change the value of this register can do it by

changing it in the BIOS. For experiments, this register can be modified in real time if

BIOS does not lock the IMC registers.

Initialization Role of CKE

During power-up, CKE is the only input to the SDRAM that has its level recognized

(other than the reset pin) once power is applied. It should be driven LOW by the DDR

controller to make sure the SDRAM components float DQ and DQS during power-up.

CKE signals remain LOW (while any reset is active) until the BIOS writes to a

configuration register. Using this method, CKE is ensured to remain inactive for much

longer than the specified 200 micro-seconds after power and clocks to SDRAM devices

are stable. In LPDDR5/DDR5, there is no CKE pin and the power management roll is

assumed by the CS signals.

5.2.2.1

Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors—Memory

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

Datasheet, Volume 1 of 2 May 2025

130 Doc. No.: 743844, Rev.: 015

Conditional Self-Refresh

During S0 idle state, system memory may be conditionally placed into self-refresh

state when the processor is in package C3 or deeper power state. Refer to Intel

Rapid Memory Power Management (Intel

RMPM) on page 71 for more details on

conditional self-refresh with Intel HD Graphics enabled.

When entering the S3 – Suspend-to-RAM (STR) state or S0 conditional self-refresh,

the processor IA core flushes pending cycles and then enters SDRAM ranks that are

not used by the processor graphics into self-refresh. The CKE signals remain LOW so

the SDRAM devices perform self-refresh.

The target behavior is to enter self-refresh for package C3 or deeper power states as

long as there are no memory requests to service.

Dynamic Power-Down

Dynamic power-down of memory is employed during normal operation. Based on idle

conditions, a given memory rank may be powered down. The IMC implements

aggressive CKE control to dynamically put the DRAM devices in a power-down state.

The processor IA core controller can be configured to put the devices in active power

down (CKE de-assertion with open pages) or pre-charge power-down (CKE de-

assertion with all pages closed). Pre-charge power-down provides greater power

savings but has a bigger performance impact, since all pages will first be closed before

putting the devices in power-down mode.

If dynamic power-down is enabled, all ranks are powered up before doing a refresh

cycle and all ranks are powered down at the end of the refresh.

DRAM I/O Power Management

Unused signals should be disabled to save power and reduce electromagnetic

interference. This includes all signals associated with an unused memory channel.

Clocks, CKE, ODT, and CS signals are controlled per DIMM rank and will be powered

down for unused ranks.

The I/O buffer for an unused signal should be tri-stated (output driver disabled), the

input receiver (differential sense-amp) should be disabled. The input path should be

gated to prevent spurious results due to noise on the unused signals (typically handled

automatically when input receiver is disabled).

DDR Electrical Power Gating

The DDR I/O of the processor supports Electrical Power Gating (DDR-EPG) while the

processor is at C3 or deeper power state.

In C3 or deeper power state, the processor internally gates VDDQ and VDD2 for the

majority of the logic to reduce idle power while keeping all critical DDR pins such as

CKE and VREF in the appropriate state.

In C7 or deeper power state, the processor internally gates VCCSA for all non-critical

state to reduce idle power.

In S3 or C-state transitions, the DDR does not go through training mode and will

restore the previous training information.

5.2.2.2

5.2.2.3

5.2.2.4

5.2.3

Memory—Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

May 2025 Datasheet, Volume 1 of 2

Doc. No.: 743844, Rev.: 015 131

Power Training

BIOS MRC performing Power Training steps to reduce DDR I/O power while keeping

reasonable operational margins still guaranteeing platform operation. The algorithms

attempt to weaken ODT, driver strength and the related buffers parameters both on

the MC and the DRAM side and find the best possible trade-off between the total I/O

power and the operating margins using advanced mathematical models.

5.2.4

Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors—Memory

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

Datasheet, Volume 1 of 2 May 2025

132 Doc. No.: 743844, Rev.: 015