743844-015.pdf - 第8页
Figures 1 S Processor Line Platform Diagram.............................................................................17 2 E/E Refresh Processor Line Platform Diagr am...................................................…
13.0 Electrical Specifications.......................................................................................... 185
13.1 Power Delivery.................................................................................................185
13.1.1 Power and Ground Pins.......................................................................... 185
13.1.2 Digital Linear Voltage Regulator (DLVR) .................................................. 185
13.1.3 V
CC
Voltage Identification (VID)...............................................................186
13.1.4 Fast V-Mode..........................................................................................186
13.1.5 Current Excursion Protection (CEP).......................................................... 187
13.2 DC Specifications.............................................................................................. 187
13.2.1 Processor Power Rails DC Specifications....................................................188
13.2.2 Processor Interfaces DC Specifications..................................................... 207
14.0 Package Mechanical Specifications......................................................................... 216
14.1 Package Mechanical Attributes............................................................................ 216
14.2 Package Storage Specifications........................................................................... 218
15.0 CPU And Device IDs................................................................................................ 219
15.1 CPUID..............................................................................................................219
15.2 PCI Configuration Header................................................................................... 220
15.3 Device IDs........................................................................................................221
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Contents—Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
May 2025 Datasheet, Volume 1 of 2
Doc. No.: 743844, Rev.: 015 7
Figures
1 S Processor Line Platform Diagram.............................................................................17
2 E/E Refresh Processor Line Platform Diagram.............................................................. 17
3 S Refresh Processor Line Platform Diagram................................................................. 18
4 P/H/H Refresh Processor Line Platform Diagram...........................................................18
5 U/U Refresh Processor Line Platform Diagram..............................................................19
6 HX /HX RefreshProcessor Line Platform Diagram.......................................................... 20
7 PX Processor Line Platform Diagram...........................................................................20
8 Example for PECI Host-Clients Connection...................................................................31
9 Example for PECI EC Connection................................................................................32
10 Device to Domain Mapping Structures ....................................................................... 36
11 Hybrid Cache.......................................................................................................... 46
12 Processor Camera System........................................................................................ 56
13 Telemetry Aggregator...............................................................................................58
14 Processor Package and IA Core C-States.....................................................................63
15 Idle Power Management Breakdown of the Processor IA Cores.......................................65
16 Package C-State Entry and Exit................................................................................. 68
17 Package Power Control............................................................................................. 78
18 PROCHOT Demotion Description ............................................................................... 84
19 Intel
®
DDR4/5 Flex Memory Technology Operations.................................................... 123
20 DDR4 Interleave (IL) and Non-Interleave (NIL) Modes Mapping....................................128
21 PCI Express* Related Register Structures in the Processor ..........................................145
22 S/S Refresh, HX/HX Refresh Processor Display Architecture......................................... 155
23 P, PX/U/U Refresh/H/H Refresh Processor Display Architecture.....................................156
24 DisplayPort* Overview............................................................................................158
25 HDMI* Overview ...................................................................................................161
26 MIPI* DSI Overview...............................................................................................163
27 Input Device Hysteresis ......................................................................................... 215
R
Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors—Figures
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
Datasheet, Volume 1 of 2 May 2025
8 Doc. No.: 743844, Rev.: 015
Tables
1 Processor Lines ...................................................................................................... 15
2 Terminology............................................................................................................26
3 Special Marks .........................................................................................................29
4 System States ........................................................................................................63
5 Integrated Memory Controller (IMC) States ................................................................64
6 G, S, and C Interface State Combinations .................................................................. 64
7 Core C-states .........................................................................................................67
8 Package C-States.................................................................................................... 68
9 Package C-States with PCIe* Link States Dependencies ............................................... 74
10 TCSS Power State ...................................................................................................74
11 Assured Power (cTDP) Modes.................................................................................... 80
12 Processor Base Power (a.k.a TDP) and Frequency Specifications Options (S-Processor
Line)......................................................................................................................89
13 Processor Base Power (a.k.a TDP) and Frequency Specifications Options (S Refresh-
Processor Line)....................................................................................................... 90
14 Processor Base Power (a.k.a TDP) and Frequency Specifications Options (HX/HX
Refresh-Processor Line)............................................................................................92
15 Processor Base Power (a.k.a TDP) and Frequency Specifications Options (U/P/H/PX/U
Refresh-Processor Line)............................................................................................95
16 Processor Base Power (a.k.a TDP) and Frequency Specifications Options (E/E Refresh
-Processor Line) ................................................................................................... 100
17 Package Turbo Specifications (S/HX/S Refresh/HX Refresh-Processor Lines) ..................101
18 Package Turbo Specifications (P/H/PX/U/U Refresh-Processor Lines) ............................ 107
19 Package Turbo Specifications (E/E Refresh Processor Lines LGA) ..................................108
20 Junction Temperature Specifications (P/H/U/U Refresh/HX/HX Refresh/PX/S/S Refresh
-Processor Lines) .................................................................................................. 110
21 Low Power and TTV Specifications (S/S Refresh-Processor Line LGA )............................110
22 Low Power and TTV Specifications (E/E Refresh Processor Line LGA) ............................ 111
23 TCONTROL Offset Configuration (S/S Refresh-Processor Line - Client) ......................... 112
24 TCONTROL Offset Configuration (E/E Refresh-Processor Line ) ................................... 112
25 DDR Support Matrix Table....................................................................................... 113
26 DDR Technology Support Matrix...............................................................................114
27 Supported DDR4 Non-ECC SoDIMM Module Configurations (S/S Refresh/H/HX/P/U/HX
Refresh/U Refresh - Processor Line)......................................................................... 115
28 Supported DDR4 ECC SoDIMM Module Configurations (S/S Refresh/HX/HX Refresh -
Processor Line) .....................................................................................................115
29 Supported DDR4 Non-ECC UDIMM Module Configurations (S/S Refresh - Processor Line) 116
30 Supported DDR4 ECC UDIMM Module Configurations (S/S Refresh - Processor Line) .......116
31 Supported DDR5 Non-ECC SoDIMM Module Configurations (S/S Refresh/H/H
Refresh/HX/P/U/HX Refresh/U Refresh - Processor Line)............................................. 116
32 Supported DDR5 ECC SoDIMM Module Configurations (S/S Refresh/HX/HX Refresh -
Processor Line) .....................................................................................................116
33 Supported DDR5 Non-ECC UDIMM Module Configurations (S/S Refresh - Processor Line) 117
34 Supported DDR5 ECC UDIMM Module Configurations (S/S Refresh/E/ /E Refresh -
Processor Line)......................................................................................................117
35 Supported DDR4 Memory Down Device Configurations (H/P/U/U Refresh - Processor
Line) ................................................................................................................... 117
36 Supported DDR5 Memory Down Device Configurations (H/P/U Refresh - Processor Line) .118
37 Supported LPDDR4x x32 DRAMs Configurations (H/P/U/U Refresh - Processor Line) ......118
38 Supported LPDDR4x x64 DRAMs Configurations (P/U/U Refresh - Processor Line)........... 118
39 Supported LPDDR5/x x32 DRAMs Configurations (H/P/PX/U/U Refresh - Processor Line) .119
40 Supported LPDDR5/x x64 DRAMs Configurations (P/PX/U/U Refresh - Processor Line)..... 119
41 DDR System Memory Timing Support....................................................................... 120
42 LPDDR System Memory Timing Support ................................................................... 120
R
Tables—Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
May 2025 Datasheet, Volume 1 of 2
Doc. No.: 743844, Rev.: 015 9