743844-015.pdf - 第46页

• For E Cores The 2nd lev el cache is shared between 4 physical cores. • The size of the LLC is SKU specific with a maximum of 3MB per P physical core or 4 E cores and is a 12-way associativ e cache. IA Cores Level 1 and…

instruction in the program stream must be an ENDBRANCH. If an ENDBRANCH is not

seen the processor causes a control protection fault (#CP), otherwise the state

machine moves back to IDLE state.

More information on Intel

CET can be found at:

https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-

enforcement-technology-preview.pdf

KeyLocker Technology

A method to make long-term keys short-lived without exposing them. This protects

against vulnerabilities when keys can be exploited and used to attack encrypted data

such as disk drives.

An instruction (LOADIWKEY) allows the OS to load a random wrapping value (IWKey).

The IWKey can be backed up and restored by the OS to/from the PCH in a secure

manner.

The Software can wrap it own key via the ENCODEKEY instruction and receive a

handle. The handle is used with the AES*KL instructions to handle encrypt and

decrypt operations. Once a handle is obtained, the software can delete the original key

from memory.

Devil’s Gate Rock

Devil’s Gate Rock (DGR) is a BIOS hardening technology that splits SMI (System

Management Interrupts) handlers into Ring 3 and Ring 0 portions.

Supervisor/user paging on the smaller Ring 0 portion will enforce access policy for all

the ring 3 code with regard to the SMM state save, MSR registers, IO ports and other

registers.

The Ring 0 portion can perform save/restore of register context to allow the Ring 3

section to make use of those registers without having access to the OS context or the

ability to modify the OS context.

The Ring 0 portion is signed and provided by Intel. This portion is attested by the

processor.

Power and Performance Technologies

Intel

Smart Cache Technology

The Intel

Smart Cache Technology is a shared Last Level Cache (LLC).

• The LLC is non-inclusive.

• The LLC may also be referred to as a 3rd level cache.

• The LLC is shared between all IA cores as well as the Processor Graphics.

• For P Cores The 1st and 2nd level caches are not shared between physical cores

and each physical core has a separate set of caches.

• For E Cores The 1st level cache is not shared between physical cores and each

physical core has a separate set of caches.

2.3.14

2.3.15

2.4

2.4.1

Technologies—Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

May 2025 Datasheet, Volume 1 of 2

Doc. No.: 743844, Rev.: 015 45

• For E Cores The 2nd level cache is shared between 4 physical cores.

• The size of the LLC is SKU specific with a maximum of 3MB per P physical core or

4 E cores and is a 12-way associative cache.

IA Cores Level 1 and Level 2 Caches

P Cores 1st level cache is divided into a data cache (DFU) and an instruction cache

(IFU). The processor 1st level cache size is 48KB for data and 32KB for instructions.

The 1st level cache is an 12-way associative cache.

E Cores 1st level cache is divided into a data cache (DFU) and an instruction cache

(IFU). The processor 1st level cache size is 32KB for data and 64KB for instructions.

The 1st level cache is an 8-way associative cache.

The 2nd level cache holds both data and instructions. It is also referred to as mid-level

cache or MLC.

For P/H/H Refresh/U, S/HX 8P+8E, S 6P+0E predecessor lines, the P Cores 2nd level

cache size is 1.25 MB and is a 10-way non-inclusive associative cache, 4 E Cores

processors 2nd level cache size is 2MB and is a 16-way non-inclusive associative

cache.

For S refresh 8P+8E, S refresh 6P+0E predecessor lines, the P Cores 2nd level cache

size is 1.25 MB and is a 10-way non-inclusive associative cache, 4 E Cores processors

2nd level cache size is 2MB and is a 16-way non-inclusive associative cache.

For S/HX 8P+16E and E Processors Lines, the P Cores 2nd level cache size is2 MB and

is a 16-way non-inclusive associative cache, 4 E Cores processors 2nd level cache size

is 4MB and is a 16-way non-inclusive associative cache.

For S Refresh/HX Refresh 8P+16E Processors Lines, the P Cores 2nd level cache size is

2 MB and is a 16-way non-inclusive associative cache, 4 E Cores processors 2nd level

cache size is 4MB and is a 16-way non-inclusive associative cache

Figure 11. Hybrid Cache

2.4.2

Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors—Technologies

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

Datasheet, Volume 1 of 2 May 2025

46 Doc. No.: 743844, Rev.: 015

NOTES

1. L1 Data cache (DCU) - 48KB (P-core) - 32KB (E-Core)

2. L1 Instruction cache (IFU) - 32KB (P-Core) - 64KB (E-Core)

3. MLC - Mid Level Cache - 2MB (P-Core) - 4MB (shared by 4 E-Cores)

Ring Interconnect

The Ring is a high speed, wide interconnect that links the processor cores, processor

graphics and the System Agent.

The Ring shares frequency and voltage with the Last Level Cache (LLC).

The Ring's frequency dynamically changes. Its frequency is relative to both processor

cores and processor graphics frequencies.

Intel

Performance Hybrid Architecture

The processor contains two types of cores, denoted as P-Cores and E-Cores (P core is

a Performance core and E core is efficient core ).

The P-Cores and E-Cores share the same instruction set.

The available instruction sets, when hybrid computing is enabled, is limited compared

to the instruction sets available to P-Cores.

P core and E core frequency's will be determined by the processor algorithmic, to

maximize performance and power optimization.

For more details, refer to: https://www.intel.com/content/www/us/en/developer/

articles/technical/hybrid-architecture.html

NOTE

Hybrid Computing may not be available on all SKUs.

Intel

Turbo Boost Max Technology 3.0

The Intel

Turbo Boost Max Technology 3.0 (ITBMT 3.0) grants a different maximum

Turbo frequency for individual processor cores.

To enable ITBMT 3.0 the processor exposes individual core capabilities; including

diverse maximum turbo frequencies.

An operating system that allows for varied per core frequency capability can then

maximize power savings and performance usage by assigning tasks to the faster

cores, especially on low core count workloads.

Processors enabled with these capabilities can also allow software (most commonly a

driver) to override the maximum per-core Turbo frequency limit and notify the

operating system via an interrupt mechanism.

2.4.3

2.4.4

2.4.5

Technologies—Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

May 2025 Datasheet, Volume 1 of 2

Doc. No.: 743844, Rev.: 015 47