743844-015.pdf - 第75页
TCSS Power State Allowed Package C Status Device Attached Description USB4 CIe is in inactive IOM is inactive IOM - TCSS Input Output Manager: • The IOM interacts with the SoC to perform power management, boot, reset, co…
PCI Express* Power Management
• Active power management support using L0s (see below), L1 Substates(L1.1,L1.2)
• L0s is supported across all PEG interfaces.
• All inputs and outputs disabled in L2/L3 Ready state.
• S Processor PCIe* interface does not support Hot-Plug.
NOTE
An increase in power consumption may be observed when PCI Express* ASPM
capabilities are disabled.
Table 9. Package C-States with PCIe* Link States Dependencies
Processor
Interface
L-State Description Package C-State
PCIe*
L1.0 or
deeper
L1- Higher latency, lower power “standby” state
L2 – Auxiliary-powered Link, deep-energy-saving
state.
Disabled - The intent of the Disabled state is to
allow a configured Link to be disabled until
directed or Electrical Idle is exited (that is, due to
a hot removal and insertion) after entering
Disabled.
No Device Attached - no physical device is
attached on PEG port
PC6-PC8
PCIe*
L1.2 or
deeper
L1- Higher latency, lower power “standby” state
L2 – Auxiliary-powered Link, deep-energy-saving
state.
Disabled - The intent of the Disabled state is to
allow a configured Link to be disabled until
directed or Electrical Idle is exited (that is, due to
a hot removal and insertion) after entering
Disabled.
No Device Attached - no physical device is
attached on PEG port
PC10
TCSS Power State
Table 10. TCSS Power State
TCSS Power
State
Allowed
Package C
Status
Device Attached Description
TC0 PC0-PC3
Yes xHCI, xDCI, USB4 controllers may be active.
USB4 DMA / PCIe may be active.
TC7 PC6-PC10
Yes xHCI and xDCI are in D3.
USB4 controller is in D3 or D0 idle.
USB4 PCIe is inactive.
TC-Cold PC3-PC10
No xHCI / xDCI / TBT DMA / TBT PCIe are in D3
IOM is active
TC10 PC6-PC10 No
Deepest Power state
xHCI and xDCI are in D3. USB4 is in D3 or D0 idle.
continued...
3.7
3.8
R
Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors—Power Management
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
Datasheet, Volume 1 of 2 May 2025
74 Doc. No.: 743844, Rev.: 015
TCSS Power
State
Allowed
Package C
Status
Device Attached Description
USB4 CIe is in inactive
IOM is inactive
IOM - TCSS Input Output Manager:
• The IOM interacts with the SoC to perform power management, boot, reset, connect and disconnect
devices to TYPE-C sub-system
TCSS Devices (xHCI / xDCI / TBT Controllers) - power states:
• D0 - Device at Active state.
• D3 - Device at lowest-powered state.
R
Power Management—Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
May 2025 Datasheet, Volume 1 of 2
Doc. No.: 743844, Rev.: 015 75
4.0 Thermal Management
Processor Thermal Management
The thermal solution provides both component-level and system-level thermal
management. To allow optimal operation and long-term reliability of Intel processor-
based systems, the system/processor thermal solution should be designed so that the
processor:
• Remains below the maximum junction temperature (Tj
MAX
) specification at the
maximum Processor Base power (a.k.a TDP).
• Conforms to system constraints, such as system acoustics, system skin-
temperatures, and exhaust-temperature requirements.
CAUTION
Thermal specifications given in this chapter are on the component and package level
and apply specifically to the processor. Operating the processor outside the specified
limits may result in permanent damage to the processor and potentially other
components in the system.
Thermal Considerations
The Processor Base Power (a.k.a TDP) is the assured sustained power that should be
used for the design of the processor thermal solution, Design to a higher thermal
capability will get more Turbo residency. Processor Base Power (a.k.a TDP) is the time-
averaged power dissipation that the processor is validated to not exceed during
manufacturing while executing an Intel-specified high complexity workload at Base
Frequency and at the maximum junction temperature for the SKU segment and
configuration.
NOTE
The System on Chip processor integrates multiple compute cores and I/O on a single
package. Platform support for specific usage experiences may require additional
concurrency power to be considered when designing the power delivery and thermal
sustained system capability.
The processor integrates multiple processing IA cores, graphics cores and for some
SKUs a PCH on a single package. This may result in power distribution differences
across the package and should be considered when designing the thermal solution.
Intel
®
Turbo Boost Technology 2.0 allows processor IA cores to run faster than the
base frequency. It is invoked opportunistically and automatically as long as the
processor is conforming to its temperature, power, power delivery, and current control
limits. When Intel
®
Turbo Boost Technology 2.0 is enabled:
4.1
4.1.1
R
Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors—Thermal Management
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
Datasheet, Volume 1 of 2 May 2025
76 Doc. No.: 743844, Rev.: 015