743844-015.pdf - 第70页

Processor deeper Package C -State entry frequency is controlled to minimiz e platform energy . When Package C -State Auto-Demotion enabled, a reduced residency in a deeper Package C -State is expected during system runs …

Package

C state

Description Dependencies

Processor Graphic in RC0 (Graphics active state) or RC6 (Graphics Core power

down state).

PKG C2

Cannot be requested explicitly by the Software.

All processor IA cores in C6 or deeper + Processor Graphic cores in RC6,

memory path may be open.

The processor will enter Package C2 when:

• Transitioning from Package C0 to deep Package C state or from deep

Package C state to Package C0.

• All IA cores requested C6 or deeper + Processor Graphic cores in RC6 but

there are constraints (LTR, programmed timer events in the near future

and so forth) prevent entry to any state deeper than C2 state.

• All IA cores requested C6 or deeper + Processor Graphic cores in RC6 but

a device memory access request is received. Upon completion of all

outstanding memory requests, the processor transitions back into a

deeper package C-state.

All processor IA cores in C6 or

deeper.

Processor Graphic cores in RC6.

PKG C3

Cannot be requested explicitly by the Software.

All cores in C6 or deeper + Processor Graphics in RC6, LLC may be flushed

and turned off, memory in self refresh, memory clock stopped.

The processor will enter Package C3 when:

• All IA cores in C6 or deeper + Processor Graphic cores in RC6.

• The platform components/devices allows proper LTR for entering Package

C3.

All processor IA cores in C6 or

deeper.

Processor Graphics in RC6.

memory in self refresh, memory

clock stopped.

LLC may be flushed and turned off.

PKG C6

Package C3 + BCLK is off + IMVP9.1 VRs voltage reduction/PSx state is

possible.

The processor will enter Package C6 when:

• All IA cores in C6 or deeper + Processor Graphic cores in RC6.

• The platform components/devices allow proper LTR for entering Package

C6.

Package C3.

BCLK is off.

IMVP9.1 VRs voltage

reduction/PSx state is possible.

PKG C8

Of all IA cores requested C8 + LLC should be flushed at once, voltage will be

removed from the LLC.

The processor will enter Package C8 when:

• All IA cores in C8 or deeper + Processor Graphic cores in RC6.

• The platform components/devices allow proper LTR for entering Package

C8.

Package C6

If all IA cores requested C8, LLC is

flushed in a

single step, voltage will be

removed from the LLC.

PKG

C10

Package C8 + display in PSR or powered, all VRs at PS4 + crystal clock off.

The processor will enter Package C10 when:

• All IA cores in C10 + Processor Graphic cores in RC6.

• The platform components/devices allow proper LTR for entering Package

C10.

Package C8.

All IA cores in C8 or deeper.

Display in PSR or powered off

All VRs at PS4.

Crystal clock off.

Note: Display In PSR is only on single embedded panel configuration and panel support PSR feature.

Package C-State Auto-Demotion

The Processor may demote the Package C-State to a shallower Package C-State to

enable better performance, for example instead of going into Package C10, processor

will demote to Package C6 (and shallower as required).

The processor's decision to demote the Package C-State is based on Power

management parameters such as required C states latencies, entry/exit energy/power,

Core wake rates, and device LTR (Latency Tolerance Report). This means that the

processor is optimized to minimize platform energy for scenarios with low idle time.

Power Management—Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

May 2025 Datasheet, Volume 1 of 2

Doc. No.: 743844, Rev.: 015 69

Processor deeper Package C-State entry frequency is controlled to minimize platform

energy. When Package C-State Auto-Demotion enabled, a reduced residency in a

deeper Package C-State is expected during system runs with high wake rates.

No change at IDLE scenario power consumption due to this feature. Package C-State

Auto-Demotion is enabled by default and controlled through BIOS menu.

Modern Standby

Modern Standby is a platform state. On display time out the OS requests the

processor to enter package C10 and platform devices at RTD3 (or disabled) in order to

attain low power in idle. Modern Standby requires proper BIOS and OS configuration.

Dynamic LLC Sizing

When all processor IA cores request C8 or deeper C-state, internal heuristics

dynamically flushes the LLC. Once the processor IA cores enter a deep C-state,

depending on their MWAIT sub-state request, the LLC is either gradually flushed N-

ways at a time or flushed all at once. Upon the processor IA cores exiting to C0 state,

the LLC is gradually expanded based on internal heuristics.

Package C-States and Display Resolutions

The integrated graphics engine has the frame buffer located in system memory. When

the display is updated, the graphics engine fetches display data from system memory.

Different screen resolutions and refresh rates have different memory latency

requirements. These requirements may limit the deepest Package C-state the

processor can enter. Other elements that may affect the deepest Package C-state

available are the following:

• Display is on or off

• Single or multiple displays

• Native or non-native resolution

• Panel Self Refresh (PSR) technology

NOTE

Display resolution is not the only factor influencing the deepest Package C-state the

processor can get into. Device latencies, interrupt response latencies, and core C-

states are among other factors that influence the final package C-state the processor

can enter.

Processor AUX Power Management

VCCIN AUX IMON Feature

This feature is the new power feature which allows the processor to read VCCIN Aux

average current via the IMVP9.1 controller over SVID.

It allows the processor to get an accurate power estimation of VCCIN Aux, which is

reflected in more accurate package power reporting and better accuracy in meeting

the package power limits (PL1, PL2, and PL3).

3.2.6

3.3

Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors—Power Management

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

Datasheet, Volume 1 of 2 May 2025

70 Doc. No.: 743844, Rev.: 015

VCCIN Aux IMON CPU strap will be enabled by default for best performance and

power.

Processor Graphics Power Management

Memory Power Savings Technologies

Intel

Rapid Memory Power Management (Intel

RMPM)

Intel

Rapid Memory Power Management (Intel

RMPM) conditionally places memory

into self-refresh when the processor is in package C3 or deeper power state to allow

the system to remain in the deeper power states longer for memory not reserved for

graphics memory. Intel

RMPM functionality depends on graphics/display state

(relevant only when processor graphics is being used), as well as memory traffic

patterns generated by other connected I/O devices.

Display Power Savings Technologies

Intel

Seamless Display Refresh Rate Switching Technology (Intel

SDRRS

Technology) with eDP* Port

Intel

DRRS provides a mechanism where the monitor is placed in a slower refresh

rate (the rate at which the display is updated). The system is smart enough to know

that the user is not displaying either 3D or media like a movie where specific refresh

rates are required. The technology is very useful in an environment such as a plane

where the user is in battery mode doing E-mail, or other standard office applications.

It is also useful where the user may be viewing web pages or social media sites while

in battery mode.

Intel

OLED Power Saving Technology (Intel

OPST) 1.1

Intel

OPST solution uses same HW infrastructure as Intel

DPST. Frames are

processed using frame change threshold based interrupt mechanism similar to Intel

DPST. Intel

OPST SW algorithm determines which pixels in the frame should be

dimmed to save power keeping visual quality (such as contrast, color) impact to

acceptable level. Since there is no backlight for OLED panels, the power savings come

solely from pixel dimming.

Intel

Display Power Saving Technology (Intel

DPST)

The Intel

DPST technique achieves back-light power savings while maintaining a

good visual experience. This is accomplished by adaptively enhancing the displayed

image while decreasing the back-light brightness simultaneously. The goal of this

technique is to provide equivalent end-user-perceived image quality at a decreased

back-light power level.

1. The original (input) image produced by the operating system or application is

analyzed by the Intel

DPST subsystem. An interrupt to Intel

DPST software is

generated whenever a meaningful change in the image attributes is detected. (A

meaningful change is when the Intel

DPST determines if the brightness of the

displaying images and the image enhancement and back-light control needs to be

altered.)

2. Intel

DPST subsystem applies an image-specific enhancement to increase image

brightness.

3.4

3.4.1

3.4.2

Power Management—Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

May 2025 Datasheet, Volume 1 of 2

Doc. No.: 743844, Rev.: 015 71