743844-015.pdf - 第126页
• LPDDR4x x16 sub-channels can be swizzled within their x32 channel • LPDDR4x x32 channels can be swizzled within their x64 MC • LPDDR5/x x16 sub-channels can be swizzle within their x64 MC • DDR4: Byte swapping is allow…
Data Scrambling
The system memory controller incorporates a Data Scrambling feature to minimize the
impact of excessive di/dt on the platform system memory VRs due to successive 1s
and 0s on the data bus. Past experience has demonstrated that traffic on the data bus
is not random and can have energy concentrated at specific spectral harmonics
creating high di/dt which is generally limited by data patterns that excite resonance
between the package inductance and on die capacitances. As a result, the system
memory controller uses a data scrambling feature to create pseudo-random patterns
on the system memory data bus to reduce the impact of any excessive di/dt.
ECC H-Matrix Syndrome Codes
Syndrome
Value
Flipped
Bit
Syndrome
Value
Flipped
Bit
Syndrome
Value
Flipped
Bit
Syndrome
Value
Flipped
Bit
0 No Error
1 64 37 26 81 2 146 53
2 65 38 46 82 18 148 4
4 66 41 61 84 34 152 20
7 60 42 9 88 50 161 49
8 67 44 16 97 21 162 1
11 36 47 23 98 38 164 17
13 27 49 63 100 54 168 33
14 3 50 47 104 5 176 44
16 68 52 14 112 52 193 8
19 55 56 30 128 71 194 24
21 10 64 70 131 22 196 40
22 29 67 6 133 58 200 56
25 45 69 42 134 13 208 19
26 57 70 62 137 28 224 11
28 0 73 12 138 41 241 7
31 15 74 25 140 48 242 31
32 69 76 32 143 43 244 59
35 39 79 51 145 37 248 35
Notes: 1. All other syndrome values indicate unrecoverable error (more than one error).
2. This table is relevant only for S-Processor ECC supported SKUs.
Data Swapping
By default, the processor supports on-board data swapping in two manners (for all
segments and DRAM technologies):
• DQ swapping is allowed within each Byte for all DDR technologies.
•
• LPDDR4x byte cannot be swizzled within their x16 sub-channel
5.1.9
5.1.10
5.1.11
R
Memory—Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
May 2025 Datasheet, Volume 1 of 2
Doc. No.: 743844, Rev.: 015 125
• LPDDR4x x16 sub-channels can be swizzled within their x32 channel
• LPDDR4x x32 channels can be swizzled within their x64 MC
• LPDDR5/x x16 sub-channels can be swizzle within their x64 MC
• DDR4: Byte swapping is allowed within each x64 Channel.
• DDR5: Byte swapping is allowed within a channel in 16-bit group: [0,1] [2,3 ].
• ECC bits swap is allowed within ECC byte/nibble: DDR4 ECC[7..0] and DDR5
ECC[3..0].
LPDDR5/x Ascending and Descending
LPDDR5/x support Ascending / descending that swap CA and CS signals connectivity
order.
Ascending Descending
CA6 CA0
CA5 CA1
CA4 CS_1
CA3 CS_0
CA2 CA2
CS_0 CA3
CS_1 CA4
CA1 CA5
CA0 CA6
NOTE
Ascending / descending can be performed in every x16 sub channel.
LPDDR4x CMD Mirroring
LPDDR4x support Mirroring that swap CA signals connectivity order.
Default Mirrored
CA 0 CA 5
CA 1 CA 4
CA 2 CA 3
CA 3 CA 2
CA 4 CA 1
CA 5 CA 0
5.1.12
5.1.13
R
Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors—Memory
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
Datasheet, Volume 1 of 2 May 2025
126 Doc. No.: 743844, Rev.: 015
NOTE
Mirroring can be performed in every x16 sub channel
DDR I/O Interleaving
NOTE
The processor supports I/O interleaving, which has the ability to swap DDR bytes for
routing considerations. BIOS configures the I/O interleaving mode before DDR
training. P-Processor line packages are optimized only for Non-Interleaving mode
(NIL).
There are two supported modes:
• Interleave (IL)
• Non-Interleave (NIL)
The following table and figure describe the pin mapping between the IL and NIL
modes.
Table 44. Interleave (IL) and Non-Interleave (NIL) Modes Pin Mapping
IL (DDR4) NIL (DDR4) DDR5 NIL(LPDDR4x) NIL(LPDDR5/x)
Channel Byte Channel Byte Channel Byte Channel Byte Channel Byte
DDR0 Byte0 DDR0 Byte0 DDR0 Byte0 DDR0 Byte0 DDR0 Byte0
DDR0 Byte1 DDR0 Byte1 DDR0 Byte1 DDR0 Byte1 DDR0 Byte1
DDR0 Byte2 DDR0 Byte4 DDR1 Byte0 DDR2 Byte0 DDR2 Byte0
DDR0 Byte3 DDR0 Byte5 DDR1 Byte1 DDR2 Byte1 DDR2 Byte1
DDR0 Byte4 DDR1 Byte0 DDR2 Byte0 DDR4 Byte0 DDR4 Byte0
DDR0 Byte5 DDR1 Byte1 DDR2 Byte1 DDR4 Byte1 DDR4 Byte1
DDR0 Byte6 DDR1 Byte4 DDR3 Byte0 DDR6 Byte0 DDR6 Byte0
DDR0 Byte7 DDR1 Byte5 DDR3 Byte1 DDR6 Byte1 DDR6 Byte1
DDR1 Byte0 DDR0 Byte2 DDR0 Byte2 DDR1 Byte0 DDR1 Byte0
DDR1 Byte1 DDR0 Byte3 DDR0 Byte3 DDR1 Byte1 DDR1 Byte1
DDR1 Byte2 DDR0 Byte6 DDR1 Byte2 DDR3 Byte0 DDR3 Byte0
DDR1 Byte3 DDR0 Byte7 DDR1 Byte3 DDR3 Byte1 DDR3 Byte1
DDR1 Byte4 DDR1 Byte2 DDR2 Byte2 DDR5 Byte0 DDR5 Byte0
DDR1 Byte5 DDR1 Byte3 DDR2 Byte3 DDR5 Byte1 DDR5 Byte1
DDR1 Byte6 DDR1 Byte6 DDR3 Byte2 DDR7 Byte0 DDR7 Byte0
DDR1 Byte7 DDR1 Byte7 DDR3 Byte3 DDR7 Byte1 DDR7 Byte1
5.1.14
R
Memory—Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
May 2025 Datasheet, Volume 1 of 2
Doc. No.: 743844, Rev.: 015 127