743844-015.pdf - 第21页
Processor Volatility Statement The processor families do not retain any end-user data when powered down and/or when the processor is physically removed. NOTE Powered down refers to the state which all processor power r a…
Figure 6. HX /HX RefreshProcessor Line Platform Diagram
CPU: 45 x 37.5 x 2.0mm
PCH: 25 x 28 x 1.7mm
BGA Type 3
eDP 1.4b
HBR3
PCIe Gen5
x16 lanes
DMI x8 Gen4
CPU
8P+16E
32EU
PCH
DP 1.4
HDMI 2.0b
x8 SATA 3.0
WiFi 6E (Gig+) -
DDR5 5600
DDR4 3200
x4 PCIe Gen4
14x USB2
10x USB3
x16 PCIe 4.0
x12 PCIe 3.0
Figure 7. PX Processor Line Platform Diagram
Notes
IO mapping shown in the block diagram
confirms its support on the RVP but default
configuration and lane sharing will be
covered in the Architecture document.
Touch Screen
(2 Nos)
Touch Pad
eDP
Connector
FPS Module
Connector
ALC711
THC – SPI (2 Nos.)
I2C
SNDW
Audio Headers
HDA / SNDW
USB2.0
ISH Sensor AIC
(MOSAIC)
Validation/Debug Hooks
· SINAI2-AVMC
· INTEC
· PnP PMR 2 x7 HDR
· TTK2.0
· TTK3.0
· SMA & SMP
PS2 KB & Mouse
Just Footprint
eSPI
MIPI60 PCH XDP
(only for PCH VISA, no
PCH JTAG)
MIPI60 Merged XDP
(CPU JTAG, CPU NOA,
PCH JTAG)
SPI
SPINOR
RPMC 32MB
SPI TPM 2.0
MDI
WiFi – BT
M.2 – Key E
x1 PCIe/CNVi
USB 2.0
WiFi Aux / BT
WiFi Main
M.2 Key E
Hybrid
Wi-Fi + BT
SSD / Optane
M.2 - Key M
x4 PCIe Gen4
x4 PCIe Slot
Foxville / SD card AIC
x2 PCIe
x1 PCIe
Embedded
Controller
Microchip MEC1521
PORT 80
· Thermal
· Discrete VR
· SMBUS HUB
· GPIO Expander
· Type C PD controller
SMBus
Scan matrix
keyboard
Camera CRD
Connector 1 (x4)
Camera CRD
Connector 2 (x2)
Battery
Charger
SPINOR
RPMC 32MB
Type-C
Type-C
Repeater
Type C
Conn. 2
HDMI ALS
HDMI
Conn.
2x Type A
Connector
2x USB3.2 Gen2x1
DDI Port 1
x8 PCIe Gen4
Type-C
Repeater
Type-C
Type C
Conn. 1
Type-C
Type-C
Repeater
Type C
Conn. 3
Repeater
Type-C
LP5/LP5x 6400 SKT
Px
DG2 COB- 128EU
IMVP9.1
VR
GDDR6
SPI Flash JTAG
Dediprog
CSI Signals
GbE LAN
JacksonVille
7560
LTE Main
LTE Aux / GNSS
SIM 1
M.2 Key B
WWAN 7560
SIM 2
M.2 - Key B
WWAN 7560 or
Keem-Bay
x2 PCIe (x1 for Wi-Fi & x2 for Keem-Bay)
eDP
Connector
DDI Port 2
uUSB Debug
connector
P PCH *
* Note
ADL-P PCH with Reduced IO
R
Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors—Introduction
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
Datasheet, Volume 1 of 2 May 2025
20 Doc. No.: 743844, Rev.: 015
Processor Volatility Statement
The processor families do not retain any end-user data when powered down and/or
when the processor is physically removed.
NOTE
Powered down refers to the state which all processor power rails are off.
Package Support
The S/S Refresh Processor lines are available in the following package:
• LGA1700
— A 45 X 37.5 mm
— Substrate Z=1.116 mm +/-0.95
— Substrate + Die Z is 1.116+0.37= 1.486 mm
The E/E Refresh-Processor line is available in the following packages:
• LGA1700
— A 45 X 37.5 mm
— Substrate Z=1.116 mm +/-0.95
— Substrate + Die Z is 1.116+0.37= 1.486 mm
The HX/HX Refresh-Processor line is available in the following packages:
• BGA1964
— A 45 X 37.5 mm
— Substrate Z = 0.594+/-0.08 mm
— 1.185±0.096 (BOTTOM OF BGA TO TOP OF DIE)
The P/H/U/U Refresh/H Refresh-Processor line is available in the following packages:
• BGA1744
— A 25 X 50 mm
— Substrate Z = 0.594+/-0.08 mm
— 1.185±0.096 (BOTTOM OF BGA TO TOP OF DIE)
The PX-Processor line is available in the following packages:
• BGA1792
— A 25 X 40 mm
— Substrate Z = 0.594+/-0.08 mm
— 1.171±0.082 (BOTTOM OF BGA TO TOP OF DIE)
Supported Technologies
• PECI – Platform Environmental Control Interface
1.1
1.2
1.3
R
Introduction—Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
May 2025 Datasheet, Volume 1 of 2
Doc. No.: 743844, Rev.: 015 21
• Intel
®
Virtualization Technology (Intel
®
VT-x)
• Intel
®
Virtualization Technology for Directed I/O (Intel
®
VT-d)
• Intel
®
APIC Virtualization Technology (Intel
®
APICv)
• Hypervisor-Managed Linear Address Translation (HLAT)
• Intel
®
Trusted Execution Technology (Intel
®
TXT)
• Intel
®
Advanced Encryption Standard New Instructions (Intel
®
AES-NI)
• PCLMULQDQ (Perform Carry-Less Multiplication Quad word) Instruction
• Intel
®
Secure Key
• Execute Disable Bit
• Intel
®
Boot Guard
• SMEP – Supervisor Mode Execution Protection
• SMAP – Supervisor Mode Access Protection
• SHA Extensions – Secure Hash Algorithm Extensions
• UMIP – User Mode Instruction Prevention
• RDPID – Read Processor ID
• Intel
®
Total Memory Encryption (Intel
®
TME)
• Intel
®
Control-flow Enforcement Technology (Intel
®
CET)
• KeyLocker Technology
• Devils gate Rock (DGR)
• Smart Cache Technology
• IA Core Level 1 and Level 2 Caches
• Intel's Performance Hybrid Architecture
• Intel
®
Turbo Boost Technology 2.0
• Intel
®
Turbo Boost Max Technology 3.0
• PAIR – Power Aware Interrupt Routing
• Intel
®
Hyper-Threading Technology (Intel
®
HT Technology)
• Intel SpeedStep
®
Technology
• Intel
®
Speed Shift Technology
• Intel
®
Advanced Vector Extensions 2 (Intel
®
AVX2)
• Intel
®
AVX2 Vector Neural Network Instructions (Intel
®
AVX2 VNNI)
• Intel
®
64 Architecture x2APIC
• Intel
®
Dynamic Tuning technology (Intel
®
DTT)
• Intel
®
GNA 3.0 (GMM and Neural Network Accelerator)
• Intel
®
Image Processing Unit (Intel
®
IPU)
• Cache Line Write Back (CLWB)
• Intel
®
Processor Trace
• Platform CrashLog
• Telemetry Aggregator
R
Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors—Introduction
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
Datasheet, Volume 1 of 2 May 2025
22 Doc. No.: 743844, Rev.: 015