743844-015.pdf - 第9页
Tables 1 Processor Lines ...................................................................................................... 15 2 T erminology...........................................................................…
Figures
1 S Processor Line Platform Diagram.............................................................................17
2 E/E Refresh Processor Line Platform Diagram.............................................................. 17
3 S Refresh Processor Line Platform Diagram................................................................. 18
4 P/H/H Refresh Processor Line Platform Diagram...........................................................18
5 U/U Refresh Processor Line Platform Diagram..............................................................19
6 HX /HX RefreshProcessor Line Platform Diagram.......................................................... 20
7 PX Processor Line Platform Diagram...........................................................................20
8 Example for PECI Host-Clients Connection...................................................................31
9 Example for PECI EC Connection................................................................................32
10 Device to Domain Mapping Structures ....................................................................... 36
11 Hybrid Cache.......................................................................................................... 46
12 Processor Camera System........................................................................................ 56
13 Telemetry Aggregator...............................................................................................58
14 Processor Package and IA Core C-States.....................................................................63
15 Idle Power Management Breakdown of the Processor IA Cores.......................................65
16 Package C-State Entry and Exit................................................................................. 68
17 Package Power Control............................................................................................. 78
18 PROCHOT Demotion Description ............................................................................... 84
19 Intel
®
DDR4/5 Flex Memory Technology Operations.................................................... 123
20 DDR4 Interleave (IL) and Non-Interleave (NIL) Modes Mapping....................................128
21 PCI Express* Related Register Structures in the Processor ..........................................145
22 S/S Refresh, HX/HX Refresh Processor Display Architecture......................................... 155
23 P, PX/U/U Refresh/H/H Refresh Processor Display Architecture.....................................156
24 DisplayPort* Overview............................................................................................158
25 HDMI* Overview ...................................................................................................161
26 MIPI* DSI Overview...............................................................................................163
27 Input Device Hysteresis ......................................................................................... 215
R
Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors—Figures
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
Datasheet, Volume 1 of 2 May 2025
8 Doc. No.: 743844, Rev.: 015
Tables
1 Processor Lines ...................................................................................................... 15
2 Terminology............................................................................................................26
3 Special Marks .........................................................................................................29
4 System States ........................................................................................................63
5 Integrated Memory Controller (IMC) States ................................................................64
6 G, S, and C Interface State Combinations .................................................................. 64
7 Core C-states .........................................................................................................67
8 Package C-States.................................................................................................... 68
9 Package C-States with PCIe* Link States Dependencies ............................................... 74
10 TCSS Power State ...................................................................................................74
11 Assured Power (cTDP) Modes.................................................................................... 80
12 Processor Base Power (a.k.a TDP) and Frequency Specifications Options (S-Processor
Line)......................................................................................................................89
13 Processor Base Power (a.k.a TDP) and Frequency Specifications Options (S Refresh-
Processor Line)....................................................................................................... 90
14 Processor Base Power (a.k.a TDP) and Frequency Specifications Options (HX/HX
Refresh-Processor Line)............................................................................................92
15 Processor Base Power (a.k.a TDP) and Frequency Specifications Options (U/P/H/PX/U
Refresh-Processor Line)............................................................................................95
16 Processor Base Power (a.k.a TDP) and Frequency Specifications Options (E/E Refresh
-Processor Line) ................................................................................................... 100
17 Package Turbo Specifications (S/HX/S Refresh/HX Refresh-Processor Lines) ..................101
18 Package Turbo Specifications (P/H/PX/U/U Refresh-Processor Lines) ............................ 107
19 Package Turbo Specifications (E/E Refresh Processor Lines LGA) ..................................108
20 Junction Temperature Specifications (P/H/U/U Refresh/HX/HX Refresh/PX/S/S Refresh
-Processor Lines) .................................................................................................. 110
21 Low Power and TTV Specifications (S/S Refresh-Processor Line LGA )............................110
22 Low Power and TTV Specifications (E/E Refresh Processor Line LGA) ............................ 111
23 TCONTROL Offset Configuration (S/S Refresh-Processor Line - Client) ......................... 112
24 TCONTROL Offset Configuration (E/E Refresh-Processor Line ) ................................... 112
25 DDR Support Matrix Table....................................................................................... 113
26 DDR Technology Support Matrix...............................................................................114
27 Supported DDR4 Non-ECC SoDIMM Module Configurations (S/S Refresh/H/HX/P/U/HX
Refresh/U Refresh - Processor Line)......................................................................... 115
28 Supported DDR4 ECC SoDIMM Module Configurations (S/S Refresh/HX/HX Refresh -
Processor Line) .....................................................................................................115
29 Supported DDR4 Non-ECC UDIMM Module Configurations (S/S Refresh - Processor Line) 116
30 Supported DDR4 ECC UDIMM Module Configurations (S/S Refresh - Processor Line) .......116
31 Supported DDR5 Non-ECC SoDIMM Module Configurations (S/S Refresh/H/H
Refresh/HX/P/U/HX Refresh/U Refresh - Processor Line)............................................. 116
32 Supported DDR5 ECC SoDIMM Module Configurations (S/S Refresh/HX/HX Refresh -
Processor Line) .....................................................................................................116
33 Supported DDR5 Non-ECC UDIMM Module Configurations (S/S Refresh - Processor Line) 117
34 Supported DDR5 ECC UDIMM Module Configurations (S/S Refresh/E/ /E Refresh -
Processor Line)......................................................................................................117
35 Supported DDR4 Memory Down Device Configurations (H/P/U/U Refresh - Processor
Line) ................................................................................................................... 117
36 Supported DDR5 Memory Down Device Configurations (H/P/U Refresh - Processor Line) .118
37 Supported LPDDR4x x32 DRAMs Configurations (H/P/U/U Refresh - Processor Line) ......118
38 Supported LPDDR4x x64 DRAMs Configurations (P/U/U Refresh - Processor Line)........... 118
39 Supported LPDDR5/x x32 DRAMs Configurations (H/P/PX/U/U Refresh - Processor Line) .119
40 Supported LPDDR5/x x64 DRAMs Configurations (P/PX/U/U Refresh - Processor Line)..... 119
41 DDR System Memory Timing Support....................................................................... 120
42 LPDDR System Memory Timing Support ................................................................... 120
R
Tables—Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
May 2025 Datasheet, Volume 1 of 2
Doc. No.: 743844, Rev.: 015 9
43 SA Speed Enhanced Speed Steps (SA-GV) and Gear Mode Frequencies ........................ 120
44 Interleave (IL) and Non-Interleave (NIL) Modes Pin Mapping ...................................... 127
45 USB-C* Port Configuration...................................................................................... 134
46 USB-C* Port Configuration...................................................................................... 134
47 USB-C* Lanes Configuration....................................................................................135
48 USB-C* Non-Supported Lane Configuration............................................................... 135
49 PCIe via USB4 Configuration................................................................................... 137
50 PCIe via USB4 Configuration................................................................................... 138
51 PCI Express* 16 - Lane Bifurcation and Lane Reversal Mapping....................................143
52 S/S Refresh/E/E Refresh /HX/HX Refresh - Processor PCI Express* 4 - Lane Reversal
Mapping .............................................................................................................. 143
53 H/H Refresh/PX PCI Express* 8 - Lane Reversal Mapping............................................ 144
54 H/H Refresh/PX/P/U/U Refresh PCI Express* 4 - Lane Reversal Mapping .......................144
55 PCI Express* Maximum Transfer Rates and Theoretical Bandwidth ...............................144
56 Hardware Accelerated Video Decoding ..................................................................... 150
57 Hardware Accelerated Video Encode ........................................................................ 151
58 Display Ports Availability and Link Rate for P, H, U - Processor Lines .............................153
59 Display Ports Availability and Link Rate for PX - Processor Lines .................................. 154
60 Display Ports Availability and Link Rate for S/S Refresh, HX/HX Refresh - Processor
Lines ...................................................................................................................154
61 Display Resolutions and Link Bandwidth for Multi-Stream Transport Calculations.............159
62 DisplayPort Maximum Resolution..............................................................................159
63 HDMI Maximum Resolution..................................................................................... 161
64 Embedded DisplayPort Maximum Resolution.............................................................. 162
65 MIPI* DSI Maximum Resolution .............................................................................. 163
66 Processor Supported Audio Formats over HDMI* and DisplayPort*................................164
67 H/H Refresh/P/U/U Refresh CSI-2 Lane Allocation Table.............................................. 166
68 PX CSI-2 Lane Allocation Table................................................................................ 167
69 Signal Tables Terminology ...................................................................................... 168
70 DDR4 Memory Interface......................................................................................... 169
71 LP4x-LP5 Memory Interface.....................................................................................170
72 DDR5 Memory Interface......................................................................................... 172
73 Error and Thermal Protection Signals........................................................................181
74 Processor Power Rails Signals ................................................................................. 182
75 Processor Ground Rails Signals ............................................................................... 183
76 GND, RSVD, and NCTF Signals.................................................................................183
77 Processor VCC
CORE
Active and Idle Mode DC Voltage and Current Specifications (S
and S-Refresh Processor Line)................................................................................. 188
78 Processor VCC
CORE
Active and Idle Mode DC Voltage and Current Specifications (HX
and HX Refresh Processor Lines).............................................................................. 192
79 Processor VCC
CORE
Active and Idle Mode DC Voltage and Current Specifications
(U/P/H/PX /U Refresh /H Refresh Processor Lines)......................................................195
80 Processor VCC
CORE
Active and Idle Mode DC Voltage and Current Specifications (E/E
Refresh Processor Line).......................................................................................... 198
81 VccIN_AUX Supply DC Voltage and Current Specifications........................................... 200
82 Processor Graphics (VccGT) Supply DC Voltage and Current Specifications.....................202
83 Memory Controller (VDD2) Supply DC Voltage and Current Specifications .................... 205
84 Vcc
1P05_PROC
Supply DC Voltage and Current Specifications.......................................... 205
85 Vcc
1P8_PROC
Supply DC Voltage and Current Specifications .......................................... 206
86 DDR4 Signal Group DC Specifications ...................................................................... 207
87 DDR5 Signal Group DC Specifications....................................................................... 208
88 LPDDR4x Signal Group DC Specifications ................................................................. 209
89 LPDDR5/x Signal Group DC Specifications ................................................................ 210
90 PCI Express* Graphics (PEG) Group DC Specifications................................................ 212
91 DSI HS Transmitter DC Specifications....................................................................... 212
R
Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors—Tables
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
Datasheet, Volume 1 of 2 May 2025
10 Doc. No.: 743844, Rev.: 015