743844-015.pdf - 第24页

Refer to P ower Management on page 62 for more information. Memory Controller Power Management • Disabling Unused System Memory Outputs • DRAM Power Management and Initialization • Initialization Role of CKE • Conditiona…

• Integrated Reference Clock PLL

NOTE

The availability of the features above may vary between different processor SKUs.

Refer to Technologies on page 30 for more information.

API Support (Windows*)

• Direct3D* 2015, Direct3D 12, Direct3D 11.2, Direct3D 11.1, Direct3D 9, Direct3D

10, Direct2D

• OpenGL* 4.5

• Open CL* 2.1, Open CL* 2.0, Open CL* 1.2, Open CL* 3.0

DirectX* extensions:

• PixelSync, Instant Access, Conservative Rasterization, Render Target Reads,

Floating-point De-norms, Shared a Virtual memory, Floating Point atomics, MSAA

sample-indexing, Fast Sampling (Coarse LOD), Quilted Textures, GPU Enqueue

Kernels, GPU Signals processing unit. Other enhancements include color

compression.

Gen 13 architecture delivers hardware acceleration of Direct X* 12 Render pipeline

comprising of the following stages: Vertex Fetch, Vertex Shader, Hull Shader,

Tessellation, Domain Shader, Geometry Shader, Rasterizer, Pixel Shader, Pixel Output.

Power Management Support

Processor Core Power Management

• Full support of ACPI C-states as implemented by the following processor C-states:

— C0, C1, C1E, C6, C8, C10

• Enhanced Intel SpeedStep

Technology

• Intel

Speed Shift Technology

Refer to Processor IA Core Power Management on page 64 for more information.

System Power Management

S/S

Refresh/E-

Processor

HX/HX

Refresh -

Processor

H/H Refresh -

Processor

P / PX -

Processor

U/U Refresh -

Processor

Generation

Intel

Core

™

Processors

and S3 MS

and S3 MS and S3 MS MS

Intel

Xeon

2400

Processors

and S3

Intel

Core

™

Generation

Processors

and S3 MS and S3 MS and S3 MS MS

Note: 1. Modern Standby

1.3.1

1.4

1.4.1

1.4.2

Introduction—Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

May 2025 Datasheet, Volume 1 of 2

Doc. No.: 743844, Rev.: 015 23

Refer to Power Management on page 62 for more information.

Memory Controller Power Management

• Disabling Unused System Memory Outputs

• DRAM Power Management and Initialization

• Initialization Role of CKE

• Conditional Self-Refresh

• Dynamic Power Down

• DRAM I/O Power Management

• DDR Electrical Power Gating (EPG)

• Power Training

Refer to Integrated Memory Controller (IMC) Power Management on page 129 for

more information

Processor Graphics Power Management

Memory Power Savings Technologies

• Intel

Rapid Memory Power Management (Intel

RMPM)

• Intel

Smart 2D Display Technology (Intel

S2DDT)

Display Power Savings Technologies

• Intel

(Seamless and Static) Display Refresh Rate Switching (DRRS) with eDP*

port

• Intel

OLED Power Saving Technology (Intel

OPST) 1.1

• Intel

Display Power Saving Technology (Intel

DPST 7.1)

• Panel Self-Refresh 2 (PSR 2)

• Low-Power Single Pipe (LPSP)

• Low-Power Dual Pipe (LPDP)

Graphics Core Power Savings Technologies

• Graphics Dynamic Frequency

• Intel

Graphics Render Standby Technology (Intel

GRST)

• Intel Capped Frames Per Second (CFPS)

Thermal Management Support

• Digital Thermal Sensor

• Intel

Adaptive Thermal Monitor

• THERMTRIP# and PROCHOT# support

• On-Demand Mode

• Memory Thermal Throttling

• External Thermal Sensor (TS-on-DIMM and TS-on-Board)

1.4.3

1.4.4

1.5

Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors—Introduction

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

Datasheet, Volume 1 of 2 May 2025

24 Doc. No.: 743844, Rev.: 015

• Render Thermal Throttling

• Fan Speed Control with DTS

• Intel

Turbo Boost Technology 2.0 Power Control

• Intel

Dynamic Tuning technology (Intel

DTT)

Refer to Thermal Management on page 76 for more information.

Ball-out Information

For information on the ballout of S/S Refresh/E download the pdf, click on the

navigation pane and refer the spreadsheet, 743844-001_S_LGA_Ballout.xlsx.

For information on H, P, U, U Refresh and H Refresh processors ball information,

download the pdf, click

on the navigation pane and refer the spreadsheet,

743844-001_HPU_Ballout.xlsx.

For information on PX processor ball information, download the pdf, click

on the

navigation pane and refer the spreadsheet, 743844-001_PX_Ballout.xlsm.

For information on HX processor ball information, download the pdf, click

on the

navigation pane and refer the spreadsheet, 743844-001_HX_Ballout.xlsx.

Processor Testability

A DCI on-board connector should be placed, to enable 13

Generation Intel

Core

™

and Intel

Generation full debug capabilities.

For 13

Generation Intel

Core

™

and Intel

Generation processor lines, a Direct

Connect Interface Tool connector is highly recommended to enable lower C-state to

debug.

The processor includes boundary-scan for board and system level testability.

Operating Systems Support

Processor Line

Windows* 11 SV2

(2022 H2)

Windows* 11 SV1

(2021 H2)

Windows* 10

(21H2/22H2)

Linux* OS Chrome* OS

Windows* Server

2022

S/S Refresh/HX/HX

Refresh -Processor Line

Yes Yes No No

P/H/U/U Refresh/H

Refresh -Processor

Lines

Yes Yes Yes No

PX-Processor Line Yes (for Windows* 11) Yes Yes No

continued...

1.6

1.7

1.8

Introduction—Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

May 2025 Datasheet, Volume 1 of 2

Doc. No.: 743844, Rev.: 015 25