743844-015.pdf - 第186页

V CC Voltage Identification (VID) Intel processors/chipsets are individually calibrated in the factory to oper ate on a specific voltage/frequency and operating-condition curv e specified for that individual processor . …

13.0 Electrical Specifications

Power Delivery

Power Rail Description

S/S Refresh/E/E

Refresh -

Processor Line

Controls

HX/HX Refresh-

Processor Line Controls

P/PX/H/H Refresh/U/U

Refresh Processor Lines

Controls

Vcc

CORE

Processor IA Cores Power

Rail

SVID SVID SVID

Vcc

Graphic Power Rail SVID SVID SVID

Vcc

IN_AUX

Support internal FIVR’s 1,

SA, PCIe, Display IO and

other internal Blocks.

PCH VID PCH VID PCH VID

Vcc

1P05_PROC

Sustain and Sustain

Gated Power Rail

Fixed Fixed Fixed

Vcc

1p8_PROC

PCIE PHY Power 1.8V Rail Fixed Fixed Fixed

Vcc

MIPILP

DDI PHY power rail for

MIPI DSI interface

------ ------ Fixed

DD2

Integrated Memory

Controller Power Rail

Fixed (Memory

technology

dependent)

Fixed (Memory technology

dependent)

Fixed (Memory technology

dependent)

Notes: 1. FIVR = Fully Integrated Voltage Regulator. For details, refer to Digital Linear Voltage Regulator (DLVR) on page

185.

2. Vcc

IN_AUX

has a few discrete voltages defined by PCH VID.

3. VCC

1P05_PROC

, for S processor the power rail is connected to a platform voltage regulator to supply power to the

sustaining power rails.

4. Vcc

MIPILP

: When MIPI DSI interface is been used, this power rail should be connected to 1.24V rail.

5. VCC

1P05_PROC

for P-Processor line power rail is connected to VCC1P05_OUT_FET rail through a power gate at

platform, to supply power to the sustain gated power rails.

Power and Ground Pins

All power pins should be connected to their respective processor power planes, while

all VSS pins should be connected to the system ground plane. Use of multiple power

and ground planes is recommended to reduce I*R drop.

Digital Linear Voltage Regulator (DLVR)

The processor has few internal DLVRs to power gate VccCore, VccGT, and VccSA power

rails.

DLVR is internal VR consumes lower power and works within a lower temperature

range.

13.1

13.1.1

13.1.2

Electrical Specifications—Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

May 2025 Datasheet, Volume 1 of 2

Doc. No.: 743844, Rev.: 015 185

Voltage Identification (VID)

Intel processors/chipsets are individually calibrated in the factory to operate on a

specific voltage/frequency and operating-condition curve specified for that individual

processor. In normal operation, the processor autonomously issues voltage control

requests according to this calibrated curve using the serial voltage-identifier (SVID)

interface. Altering the voltage applied at the processor/chipset causing operation

outside of this calibrated curve is considered out-of-specification operation.

The SVID bus consists of three open-drain signals: clock, data, and alert# to both set

voltage-levels and gather telemetry data from the voltage regulators. Voltages are

controlled per an 8-bit integer value, called a VID, that maps to an analog voltage

level. An offset field also exists that allows altering the VID table. Alert can be used to

inform the processor that a voltage-change request has been completed or to

interrupt the processor with a fault notification.

For VID coding and further information, refer to the IMVP9.1 (FVM feature support

version) PWM Specification and Serial VID (SVID) Protocol Specification .

Fast V-Mode

An SoC integrated detector monitors when the SoC load current exceeds a preset

threshold by monitoring for SoC voltage domain voltage droop. The SoC compares the

IMVP VR output voltage with a preset threshold voltage (Vtrip) and when the IMVP VR

output voltage reached this Vtrip, the SoC throttles itself to reduce the SoC load

current.

IMVP9.1 VRs enhance this detector by adding a cycle-by-cycle current limiting feature

where the IMVP VR quickly enters cycle by cycle current limit (becomes a current

source) with the VR output current limited to a preset value (I TRIP ) as set in the VR

ICC_limit register

Terminology

1. IccMax is the maximum current the processor can draw, typically seen running a

virus application (stress applications specifically designed to push the SoC to

maximum power). This is the current used to design the voltage regulator

decoupling.

2. PMax (PL4) is the maximum instantaneous electrical power drawn by the SoC

(per power rail), typically seen running a virus app (stress applications specifically

designed to reach maximum consumed power) with an all core turbo and Tjmax

scenario.

3. IccMax.app is less than IccMax and is the electrical current drawn by the SoC

(per power rail) while running a typical user realistic application(s) scenario at

P0nmax and Tjmax. It corresponds to PMax.App.

4. PMax.App (PL4.App) is less than PMax and is the power drawn by the SoC (per

power rail) while running a typical user realistic application(s) scenario at P0nmax

and Tjmax. It corresponds to IccMax.App.

5. I

TRIP

is VR output current limit threshold above which the VR goes into current

limit. This current is greater than IccMax.App and less than IccMax. It is

determined by customer-specific VR current capability and the VR IMON

measurement tolerance (TOL IMON).

Generally, I

TRIP

= IccMax.App/(1-TOLI MON ). Setting I

TRIP

this way guarantees

the VR never goes into current limit below IccMax.APP.

13.1.3

13.1.4

Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors—Electrical Specifications

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

Datasheet, Volume 1 of 2 May 2025

186 Doc. No.: 743844, Rev.: 015

6. I

TRIPMax

is the peak current the VR FETs and inductors could see accounting for

the VR controller current measurement tolerance (TOL IMON ). The SoC VR and

system input power sources must be able to sustain this current for at least 10ms.

NOTE

TOL_IMON can be sometimes called as ITRIP_TOL or ITRIP_ACCURACY

7. V

TRIP

is the output voltage level below which the SoC will self-throttle. In

application, this voltage is internally set in the SoC and is not visible external to

the SoC. For the purposes of VRTT testing, a Vtrip will be provided for use with the

Python* test script used for FVM testing

Benefits

• The SoC droop detector and IMVP cycle by cycle limiting work together to allow

the voltage regulator inductors and FETs to be sized for realistic workload current

(~ICCMAX.APP) instead of virus currents (ICCMAX)

• Allows power sources to be sized for realistic workload currents, by shielding them

from SoC large dynamic loading events that occur when the SoC current exceeds

the worst case realistic maximum current (ICCMAX.APP).

Current Excursion Protection (CEP)

This power management is a Processor integrated detector that senses when the

Processor load current exceeds a preset threshold by monitoring for a Processor power

domain voltage droop at the Processor power domain IMVPVR sense point. The

Processor compares the IMVPVR output voltage with a preset threshold voltage (V

TRIP

)

and when the IMVPVR output voltage is equal to or less than V

TRIP

, the Processor

internally throttles itself to reduce the Processor load current and the power

DC Specifications

The processor DC specifications in this section are defined at the processor signal pins,

unless noted otherwise. For pin listing, refer to Package Ballout Mechanical

Specification:

•

for S/S Refresh/E/E Refresh -Processor line,download the pdf, click

on the

navigation pane and refer the spreadsheet, 743844-001_S_LGA_Ballout.xlsx.

•

for HX/HX Refresh-Processor line, download the pdf, click

on the navigation

pane and refer the spreadsheet, 743844-001_HX_Ballout.xlsm.

•

for H/H Refresh/P/U/U Refresh-Processor line, download the pdf, click

on the

navigation pane and refer the spreadsheet, 743844-001_HPU_Ballout.xlsm.

•

for PX-Processor line, download the pdf, click

on the navigation pane and refer

the spreadsheet, 743844-001_PX_Ballout.xlsm.

• The DC specifications for the DDR4/DDR5/LPDDR4x/LPDDR5/x signals are listed in

the Voltage and Current Specifications section.

• The Voltage and Current Specifications section lists the DC specifications for the

processor and are valid only while meeting specifications for junction temperature,

clock frequency, and input voltages. Read all notes associated with each

parameter.

13.1.5

13.2

Electrical Specifications—Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

May 2025 Datasheet, Volume 1 of 2

Doc. No.: 743844, Rev.: 015 187