743844-015.pdf - 第5页

4.1.4 Intel ® Memory Thermal Management ......................................................... 87 4.2 General Notes......................................................................................................…

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2.4.5 Intel
®
Turbo Boost Max Technology 3.0........................................................47
2.4.6 Power Aware Interrupt Routing (PAIR)......................................................... 48
2.4.7 Intel
®
Hyper-Threading Technology............................................................. 48
2.4.8 Intel
®
Turbo Boost Technology 2.0.............................................................. 48
2.4.9 Enhanced Intel SpeedStep
®
Technology....................................................... 49
2.4.10 Intel
®
Thermal Velocity Boost (Intel
®
TVB)..................................................50
2.4.11 Intel
®
Speed Shift Technology ..................................................................50
2.4.12 Intel
®
Advanced Vector Extensions 2 (Intel
®
AVX2) .................................... 50
2.4.13 Intel
®
64 Architecture x2APIC...................................................................51
2.4.14 Intel
®
Dynamic Tuning Technology............................................................ 52
2.4.15 Intel
®
GMM and Neural Network Accelerator................................................52
2.4.16 Cache Line Write Back............................................................................. 54
2.4.17 Remote Action Request............................................................................ 54
2.4.18 User Mode Wait Instructions .................................................................... 54
2.4.19 Intel
®
Adaptive Boost Technology..............................................................55
2.5 Intel
®
Image Processing Unit.................................................................................. 55
2.5.1 Platform Imaging Infrastructure..................................................................55
2.5.2 Intel
®
Image Processing Unit...................................................................... 56
2.6 Debug Technologies ............................................................................................. 56
2.6.1 Intel
®
Processor Trace .............................................................................. 56
2.6.2 Platform CrashLog.....................................................................................57
2.6.3 Telemetry Aggregator................................................................................ 57
2.7 Clock Topology..................................................................................................... 58
2.7.1 Integrated Reference Clock PLL...................................................................59
2.8 Intel Volume Management Device Technology .......................................................... 59
2.9 Deprecated Technologies........................................................................................61
3.0 Power Management.................................................................................................... 62
3.1 Advanced Configuration and Power Interface (ACPI) States Supported......................... 63
3.2 Processor IA Core Power Management..................................................................... 64
3.2.1 OS/HW Controlled P-states.........................................................................65
3.2.2 Low-Power Idle States............................................................................... 65
3.2.3 Requesting the Low-Power Idle States......................................................... 66
3.2.4 Processor IA Core C-State Rules..................................................................66
3.2.5 Package C-States......................................................................................67
3.2.6 Package C-States and Display Resolutions.................................................... 70
3.3 Processor AUX Power Management ........................................................................70
3.4 Processor Graphics Power Management ...................................................................71
3.4.1 Memory Power Savings Technologies........................................................... 71
3.4.2 Display Power Savings Technologies............................................................ 71
3.4.3 Processor Graphics Core Power Savings Technologies.....................................72
3.5 System Agent Enhanced Intel SpeedStep
®
Technology...............................................73
3.6 Rest Of Platform (ROP) PMIC ................................................................................. 73
3.7 PCI Express* Power Management............................................................................74
3.8 TCSS Power State................................................................................................ 74
4.0 Thermal Management................................................................................................. 76
4.1 Processor Thermal Management..............................................................................76
4.1.1 Thermal Considerations............................................................................. 76
4.1.2 Assured Power (cTDP) .............................................................................. 79
4.1.3 Thermal Management Features................................................................... 80
R
Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors—Contents
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
Datasheet, Volume 1 of 2 May 2025
4 Doc. No.: 743844, Rev.: 015
4.1.4 Intel
®
Memory Thermal Management ......................................................... 87
4.2 General Notes...................................................................................................... 88
4.3 Processor Line Power and Frequency Specifications....................................................89
4.4 Processor Line Thermal and Power Specifications.....................................................101
5.0 Memory.....................................................................................................................113
5.1 System Memory Interface.................................................................................... 113
5.1.1 Processor SKU Support Matrix...................................................................113
5.1.2 Supported Memory Modules and Devices.................................................... 115
5.1.3 System Memory Timing Support................................................................119
5.1.4 Memory Controller (MC)...........................................................................122
5.1.5 Memory Controller Power Gate..................................................................122
5.1.6 System Memory Controller Organization Mode (DDR4/5 Only)....................... 122
5.1.7 System Memory Frequency.......................................................................124
5.1.8 Technology Enhancements of Intel
®
FMA.................................................... 124
5.1.9 Data Scrambling..................................................................................... 125
5.1.10 ECC H-Matrix Syndrome Codes................................................................125
5.1.11 Data Swapping .....................................................................................125
5.1.12 LPDDR5/x Ascending and Descending.......................................................126
5.1.13 LPDDR4x CMD Mirroring......................................................................... 126
5.1.14 DDR I/O Interleaving............................................................................. 127
5.1.15 DRAM Clock Generation .........................................................................128
5.1.16 DRAM Reference Voltage Generation ....................................................... 128
5.1.17 Data Swizzling...................................................................................... 128
5.1.18 Error Correction With Standard RAM........................................................ 128
5.1.19 Post Package Repair ..............................................................................128
5.1.20 Refresh Management (RFM).................................................................... 129
5.2 Integrated Memory Controller (IMC) Power Management.......................................... 129
5.2.1 Disabling Unused System Memory Outputs................................................. 129
5.2.2 DRAM Power Management and Initialization................................................ 129
5.2.3 DDR Electrical Power Gating..................................................................... 131
5.2.4 Power Training........................................................................................ 132
6.0 USB-C* Sub System.................................................................................................. 133
6.1 General Capabilities.............................................................................................133
6.2 USB* 4 Router....................................................................................................135
6.2.1 USB 4 Host Router Implementation Capabilities...........................................136
6.3 USB-C Sub-system xHCI/xDCI Controllers.............................................................. 137
6.3.1 USB 3 Controllers....................................................................................137
6.3.2 USB-C Sub-System PCIe Interface.............................................................137
6.4 USB-C Sub-System Display Interface..................................................................... 138
7.0 PCIe* Interface........................................................................................................ 139
7.1 Processor PCI Express* Interface.......................................................................... 139
7.1.1 PCI Express* Support.............................................................................. 139
7.1.2 PCI Express* Architecture........................................................................ 145
7.1.3 PCI Express* Configuration Mechanism ..................................................... 145
7.1.4 PCI Express* Equalization Methodology .....................................................146
7.1.5 PCI Express* Hot Plug............................................................................ 146
8.0 Direct Media Interface and On Package Interface..................................................... 147
8.1 Direct Media Interface (DMI)................................................................................ 147
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Contents—Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
May 2025 Datasheet, Volume 1 of 2
Doc. No.: 743844, Rev.: 015 5
8.1.1 DMI Error Flow........................................................................................147
8.1.2 DMI Link Down....................................................................................... 147
8.2 On Package Interface (OPI).................................................................................. 147
8.2.1 OPI Support........................................................................................... 147
8.2.2 Functional Description..............................................................................148
9.0 Graphics....................................................................................................................149
9.1 Processor Graphics..............................................................................................149
9.1.1 Media Support (Intel
®
QuickSync and Clear Video Technology HD)................. 149
9.1.2 Platform Graphics Hardware Feature ......................................................... 152
10.0 Display.................................................................................................................... 153
10.1 Display Technologies Support..............................................................................153
10.2 Display Configuration.........................................................................................153
10.3 Display Features................................................................................................157
10.3.1 General Capabilities............................................................................... 157
10.3.2 Multiple Display Configurations................................................................157
10.3.3 High-bandwidth Digital Content Protection (HDCP)..................................... 157
10.3.4 DisplayPort*......................................................................................... 158
10.3.5 High-Definition Multimedia Interface (HDMI*)........................................... 160
10.3.6 embedded DisplayPort* (eDP*)............................................................... 162
10.3.7 MIPI* DSI............................................................................................ 162
10.3.8 Integrated Audio................................................................................... 163
11.0 Camera/MIPI.......................................................................................................... 165
11.1 Camera Pipe Support......................................................................................... 165
11.2 MIPI* CSI-2 Camera Interconnect....................................................................... 165
11.2.1 Camera Control Logic.............................................................................166
11.2.2 Camera Modules....................................................................................166
11.2.3 CSI-2 Lane Configurations...................................................................... 166
12.0 Signal Description................................................................................................... 168
12.1 System Memory Interface...................................................................................169
12.1.1 DDR4 Memory Interface......................................................................... 169
12.1.2 LP4x-LP5 Memory Interface.................................................................... 170
12.1.3 DDR5 Memory Interface......................................................................... 172
12.2 PCI Express* Graphics (PEG) Signals................................................................... 174
12.3 Direct Media Interface (DMI) Signals....................................................................174
12.4 Reset and Miscellaneous Signals.......................................................................... 175
12.5 Display Interfaces .............................................................................................177
12.5.1 Digital Display Interface (DDI) Signals..................................................... 177
12.5.2 Digital Display Audio Signals................................................................... 178
12.6 USB Type-C Signals........................................................................................... 178
12.7 MIPI CSI 2 Interface Signals............................................................................... 179
12.8 Processor Clocking Signals..................................................................................180
12.9 Testability and Monitoring Signals........................................................................ 180
12.10 Error and Thermal Protection Signals..................................................................181
12.11 Processor Power Rails.......................................................................................182
12.12 Ground and Reserved Signals............................................................................183
12.13 Processor Internal Pull-Up / Pull- Down on Package ............................................. 184
R
Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors—Contents
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
Datasheet, Volume 1 of 2 May 2025
6 Doc. No.: 743844, Rev.: 015