743844-015.pdf - 第160页

Standard PX, H-Processor Line U/U Refresh , P - Processor Line 7680x4320 60Hz 30bpp 7680x4320 60Hz 30bpp Notes: 1. Maximum resolution is based on the implementation of 4 lanes at highest link data rate supported. 2. bpp …

Table 61. Display Resolutions and Link Bandwidth for Multi-Stream Transport

Calculations

Pixels per Line Lines

Refresh Rate

[Hz]

Pixel Clock [MHz]

Link Bandwidth

[Gbps]

1920 1080 60 148.5 4.46

1920 1200 60 154 4.62

2048 1152 60 156.75 4.70

2048 1280 60 174.25 5.23

2048 1536 60 209.25 6.28

2304 1440 60 218.75 6.56

2560 1440 60 241.5 7.25

3840 2160 30 262.75 7.88

2560 1600 60 268.5 8.06

2880 1800 60 337.5 10.13

3200 2400 60 497.75 14.93

3840 2160 60 533.25 16.00

4096 2160 60 556.75 16.70

4096 2304 60 605 18.15

5120 3200 60 1042.5 31.28

Notes: 1. All the above is related to bit depth of 24.

2. The data rate for a given video mode can be calculated as- Data Rate = Pixel Frequency * Bit

Depth.

3. The bandwidth requirements for a given video mode can be calculated as: Bandwidth = Data

Rate * 1.25 (for 8b/10b coding overhead).

4. The link bandwidth depends if the standards is reduced blanking or not.

If the standard is not reduced blanking - the expected bandwidth may be higher.

For more details, refer to VESA and Industry Standards and Guidelines for Computer Display

Monitor Timing (DMT). Version 1.0, Rev. 13 February 8, 2013

5. To calculate what are the resolutions that can be supported in MST configurations, follow the

below guidelines:

a. Identify what is the link bandwidth column according to the requested display resolution.

b. Summarize the bandwidth for two of three displays accordingly, and make sure the final

result is below 21.6 Gbps. (for example: 4 lanes HBR2 bit rate)

For example:

a. Docking two displays: 3840x2160@60 Hz + 1920x1200@60hz = 16 + 4.62 = 20.62 Gbps

[Supported]

b. Docking three displays: 3840x2160@30 Hz + 3840x2160@30 Hz + 1920x1080@60 Hz =

7.88 + 7.88 + 4.16 = 19.92 Gbps [Supported].

Table 62. DisplayPort Maximum Resolution

Standard PX, H-Processor Line

U/U Refresh , P -

Processor Line

DP* 4096x2304 60Hz 36bpp

5120x3200 60Hz 24bpp

4096x2304 60Hz 36bpp

5120x3200 60Hz 24bpp

DP* with DSC

5120x3200 120Hz 30bpp 5120x3200 120Hz 30bpp

continued...

Display—Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

May 2025 Datasheet, Volume 1 of 2

Doc. No.: 743844, Rev.: 015 159

Standard PX, H-Processor Line

U/U Refresh , P -

Processor Line

7680x4320 60Hz 30bpp 7680x4320 60Hz 30bpp

Notes: 1. Maximum resolution is based on the implementation of 4 lanes at highest link data rate

supported.

2. bpp - bit per pixel.

3. Resolution support is subject to memory BW availability.

4. Resolutions may consume two display pipes.

Standard S/S Refresh, HX/HX Refresh - Processor Line

DP* 4096x2304 60 Hz 36 bpp

5120x3200 60 Hz 24 bpp

DP* with DSC

5120x3200 120 Hz 30 bpp

7680x4320 60 Hz 30 bpp

Notes: 1. Maximum resolution is based on the implementation of 4 lanes at HBR3 link data rate.

2. bpp - bit per pixel.

3. Resolution support is subject to memory BW availability.

4. Resolutions may consume two display pipes.

High-Definition Multimedia Interface (HDMI*)

The High-Definition Multimedia Interface (HDMI*) is provided for transmitting

uncompressed digital audio and video signals from DVD players, set-top boxes, and

other audio-visual sources to television sets, projectors, and other video displays. It

can carry high-quality multi-channel audio data and all standard and high-definition

consumer electronics video formats. The HDMI display interface connecting the

processor and display devices uses transition minimized differential signaling (TMDS)

to carry audiovisual information through the same HDMI cable.

HDMI* includes three separate communications channels: TMDS, DDC, and the

optional CEC (consumer electronics control). CEC is not supported on the processor.

As shown in the following figure, the HDMI* cable carries four differential pairs that

make up the TMDS data and clock channels. These channels are used to carry video,

audio, and auxiliary data. In addition, HDMI carries a VESA DDC. The DDC is used by

an HDMI* Source to determine the capabilities and characteristics of the Sink.

Audio, video, and auxiliary (control/status) data is transmitted across the three TMDS

data channels. The video pixel clock is transmitted on the TMDS clock channel and is

used by the receiver for data recovery on the three data channels. The digital display

data signals driven natively through the PCH are AC coupled and needs level shifting

to convert the AC coupled signals to the HDMI* compliant digital signals. The

processor HDMI* interface is designed in accordance with the High-Definition

Multimedia Interface.

10.3.5

Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors—Display

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

Datasheet, Volume 1 of 2 May 2025

160 Doc. No.: 743844, Rev.: 015

Figure 25. HDMI* Overview

HDMI Source

HDMI Sink

TMDS Data Channel 0

Hot-Plug Detect

HDMI Tx

(Processor)

HDMI Rx

TMDS

Data

Channel

TMDS Data Channel 2

TMDS Clock Channel

CEC Line (optional)

Display Data Channel (DDC)

• DDC (Display Data Channel) channel.

• Support YCbCR 4:4:4, YCbCR 4:2:0, YCbCR 4:2:2, and RGB color format.

• Support up to 36 BPP (Bit Per Pixel).

• Hot Plug Detect.

Table 63. HDMI Maximum Resolution

Standard

PX, H/H Refresh - Processor

Line

P, U/U Refresh - Processor

Line

HDMI 1.4 4Kx2K 24-30 Hz 24bpp 4Kx2K 24-30 Hz 24bpp

HDMI 2.1 TMDS Compatible 4Kx2K 48-60Hz 24bpp (RGB/

YUV444)

4Kx2K 48-60Hz 12bpc (YUV420)

4Kx2K 48-60Hz 24bpp (RGB/

YUV444)

4Kx2K 48-60Hz 12bpc (YUV420)

Notes: 1. bpp - bit per pixel.

2. Resolution support is subject to memory BW availability.

3. HDMI2.1 can be supported using PCON (DP1.4 to HDMI2.1 protocol converter).

Standard S/S Refresh, HX/HX Refresh - Processor Line

HDMI 1.4 4Kx2K 24-30 Hz 24 bpp

HDMI 2.1 TMDS Compatible 4Kx2K 48-60 Hz 24 bpp (RGB/YUV444)

4Kx2K 48-60 Hz 12 bpc (YUV420)

Notes: 1. bpp - bit per pixel.

2. Resolution support is subject to memory BW availability.

3. HDMI2.1 can be supported using PCON (DP1.4 to HDMI2.1 protocol converter).

Display—Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

May 2025 Datasheet, Volume 1 of 2

Doc. No.: 743844, Rev.: 015 161