743844-015.pdf - 第161页
Figure 25. HDMI* Overview HDMI Source HDMI Sink TMDS Data Channel 0 Hot-Plug De tect HDMI T x (Processor) HDMI Rx TMDS Data Channel 1 TMDS Data Channel 2 TMDS Clock Channel CEC Line (optional) Display Dat a Channel (DDC)…
Standard PX, H-Processor Line
U/U Refresh , P -
Processor Line
7680x4320 60Hz 30bpp 7680x4320 60Hz 30bpp
Notes: 1. Maximum resolution is based on the implementation of 4 lanes at highest link data rate
supported.
2. bpp - bit per pixel.
3. Resolution support is subject to memory BW availability.
4. Resolutions may consume two display pipes.
Standard S/S Refresh, HX/HX Refresh - Processor Line
DP* 4096x2304 60 Hz 36 bpp
5120x3200 60 Hz 24 bpp
DP* with DSC
4
5120x3200 120 Hz 30 bpp
7680x4320 60 Hz 30 bpp
Notes: 1. Maximum resolution is based on the implementation of 4 lanes at HBR3 link data rate.
2. bpp - bit per pixel.
3. Resolution support is subject to memory BW availability.
4. Resolutions may consume two display pipes.
High-Definition Multimedia Interface (HDMI*)
The High-Definition Multimedia Interface (HDMI*) is provided for transmitting
uncompressed digital audio and video signals from DVD players, set-top boxes, and
other audio-visual sources to television sets, projectors, and other video displays. It
can carry high-quality multi-channel audio data and all standard and high-definition
consumer electronics video formats. The HDMI display interface connecting the
processor and display devices uses transition minimized differential signaling (TMDS)
to carry audiovisual information through the same HDMI cable.
HDMI* includes three separate communications channels: TMDS, DDC, and the
optional CEC (consumer electronics control). CEC is not supported on the processor.
As shown in the following figure, the HDMI* cable carries four differential pairs that
make up the TMDS data and clock channels. These channels are used to carry video,
audio, and auxiliary data. In addition, HDMI carries a VESA DDC. The DDC is used by
an HDMI* Source to determine the capabilities and characteristics of the Sink.
Audio, video, and auxiliary (control/status) data is transmitted across the three TMDS
data channels. The video pixel clock is transmitted on the TMDS clock channel and is
used by the receiver for data recovery on the three data channels. The digital display
data signals driven natively through the PCH are AC coupled and needs level shifting
to convert the AC coupled signals to the HDMI* compliant digital signals. The
processor HDMI* interface is designed in accordance with the High-Definition
Multimedia Interface.
10.3.5
R
Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors—Display
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
Datasheet, Volume 1 of 2 May 2025
160 Doc. No.: 743844, Rev.: 015
Figure 25. HDMI* Overview
HDMI Source
HDMI Sink
TMDS Data Channel 0
Hot-Plug Detect
HDMI Tx
(Processor)
HDMI Rx
TMDS
Data
Channel
1
TMDS Data Channel 2
TMDS Clock Channel
CEC Line (optional)
Display Data Channel (DDC)
• DDC (Display Data Channel) channel.
• Support YCbCR 4:4:4, YCbCR 4:2:0, YCbCR 4:2:2, and RGB color format.
• Support up to 36 BPP (Bit Per Pixel).
• Hot Plug Detect.
Table 63. HDMI Maximum Resolution
Standard
PX, H/H Refresh - Processor
Line
P, U/U Refresh - Processor
Line
HDMI 1.4 4Kx2K 24-30 Hz 24bpp 4Kx2K 24-30 Hz 24bpp
HDMI 2.1 TMDS Compatible 4Kx2K 48-60Hz 24bpp (RGB/
YUV444)
4Kx2K 48-60Hz 12bpc (YUV420)
4Kx2K 48-60Hz 24bpp (RGB/
YUV444)
4Kx2K 48-60Hz 12bpc (YUV420)
Notes: 1. bpp - bit per pixel.
2. Resolution support is subject to memory BW availability.
3. HDMI2.1 can be supported using PCON (DP1.4 to HDMI2.1 protocol converter).
Standard S/S Refresh, HX/HX Refresh - Processor Line
HDMI 1.4 4Kx2K 24-30 Hz 24 bpp
HDMI 2.1 TMDS Compatible 4Kx2K 48-60 Hz 24 bpp (RGB/YUV444)
4Kx2K 48-60 Hz 12 bpc (YUV420)
Notes: 1. bpp - bit per pixel.
2. Resolution support is subject to memory BW availability.
3. HDMI2.1 can be supported using PCON (DP1.4 to HDMI2.1 protocol converter).
R
Display—Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
May 2025 Datasheet, Volume 1 of 2
Doc. No.: 743844, Rev.: 015 161
embedded DisplayPort* (eDP*)
The embedded DisplayPort* (eDP*) is an embedded version of the DisplayPort
standard oriented towards applications such as notebook and All-In-One PCs. Like
DisplayPort, embedded DisplayPort* also consists of the Main Link, Auxiliary channel,
and an optional Hot-Plug Detect signal.
• Supported on Low power optimized pipes.
• Support up to HBR3 link rate.
• Support Backlight PWM control and enable signals, and power enable.
• Support VESA DSC 1.1.
• Support SSC.
• Panel Self Refresh 1.
• Panel Self Refresh 2
• MSO 2x2 (Multi Segment Operation).
• Adaptive Sync.
Table 64. Embedded DisplayPort Maximum Resolution
Standard PX, H - Processor Line
P, U/U Refresh - Processor
Line
eDP* 4096x2304 60Hz 36bpp
5120x3200 60Hz 24bpp
4096x2304 60Hz 36bpp
5120x3200 60Hz 24bpp
eDP* with DSC
5
5120x3200 120Hz 30bpp 5120x3200 120Hz 30bpp
Notes: 1. Maximum resolution is based on the implementation of 4 lanes at HBR3 link data rate.
2. PSR2 supported for P and M processor lines only and up to 5 K resolutions.
3. bpp - bit per pixel.
4. Resolution support is subject to memory BW availability.
5. High resolution panels supporting Display Stream Compression (DSC) are supported,
technology enablement may be limited due to low market availability.
Standard S/S Refresh, HX/HX Refresh - Processor Line
1
eDP* 4096x2304 60 Hz 36 bpp
5120x3200 60 Hz 24 bpp
eDP* with DSC
5
5120x3200 120 Hz 30 bpp
Notes: 1. Maximum resolution is based on the implementation of 4 lanes at HBR3 link data rate.
2. bpp - bit per pixel.
3. Resolution support is subject to memory BW availability.
4. High resolution panels supporting Display Stream Compression (DSC) are supported,
technology enablement may be limited due to low market availability.
MIPI* DSI
Display Serial Interface (DSI*) specifies the interface between a host processor and
peripherals such as a display module. DSI is a high speed and high performance serial
interface that offers efficient and low power connectivity between the processor and
the display module.
• One link x8 data lanes or two links each with x4 lanes support.
• Supported on Low power optimized pipes.
10.3.6
10.3.7
R
Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors—Display
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
Datasheet, Volume 1 of 2 May 2025
162 Doc. No.: 743844, Rev.: 015