743844-015.pdf - 第39页

The guest paging structure managed by the guest OS specifies the ordinary translation of a guest linear address to the guest physical address and attributes that the guest ring-0 software has programmed, whereas HLA T sp…

Intel

APIC Virtualization Technology (Intel

APICv)

APIC virtualization is a collection of features that can be used to support the

virtualization of interrupts and the Advanced Programmable Interrupt Controller

(APIC).

When APIC virtualization is enabled, the processor emulates many accesses to the

APIC, tracks the state of the virtual APIC, and delivers virtual interrupts — all in VMX

non-root operation without a VM exit.

The following are the VM-execution controls relevant to APIC virtualization and virtual

interrupts:

• Virtual-interrupt Delivery. This controls enables the evaluation and delivery of

pending virtual interrupts. It also enables the emulation of writes (memory-

mapped or MSR-based, as enabled) to the APIC registers that control interrupt

prioritization.

• Use TPR Shadow. This control enables emulation of accesses to the APIC’s task-

priority register (TPR) via CR8 and, if enabled, via the memory-mapped or MSR-

based interfaces.

• Virtualize APIC Accesses. This control enables virtualization of memory-mapped

accesses to the APIC by causing VM exits on accesses to a VMM-specified APIC-

access page. Some of the other controls, if set, may cause some of these accesses

to be emulated rather than causing VM exits.

• Virtualize x2APIC Mode. This control enables virtualization of MSR-based

accesses to the APIC.

• APIC-register Virtualization. This control allows memory-mapped and MSR-

based reads of most APIC registers (as enabled) by satisfying them from the

virtual-APIC page. It directs memory-mapped writes to the APIC-access page to

the virtual-APIC page, following them by VM exits for VMM emulation.

• Process Posted Interrupts. This control allows software to post virtual

interrupts in a data structure and send a notification to another logical processor;

upon receipt of the notification, the target processor will process the posted

interrupts by copying them into the virtual-APIC page.

NOTE

Intel

APIC Virtualization Technology may not be available on all SKUs.

Intel

APIC Virtualization specifications and functional descriptions are included in the

Intel

64 Architectures Software Developer’s Manual, Volume 3. Available at:

http://www.intel.com/products/processor/manuals

Hypervisor-Managed Linear Address Translation

Hypervisor-Managed Linear Address Translation (HLAT) is active when the “enable

HLAT” VM-execution control is 1. The processor looks up the HLAT if, during a guest

linear address translation, the guest linear address matches the Protected Linear

Range. The lookup from guest linear addresses to the guest physical address and

attributes is determined by a set of HLAT paging structures.

2.2.3

2.2.4

Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors—Technologies

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

Datasheet, Volume 1 of 2 May 2025

38 Doc. No.: 743844, Rev.: 015

The guest paging structure managed by the guest OS specifies the ordinary

translation of a guest linear address to the guest physical address and attributes that

the guest ring-0 software has programmed, whereas HLAT specifies the alternate

translation of the guest linear address to guest physical address and attributes that

the Secure Kernel and VMM seek to enforce. A logical processor uses HLAT to translate

guest linear addresses only when those guest linear addresses are used to access

memory (both for code fetch and data load/store) and the guest linear addresses

match the PLR programmed by the VMM/Secure Kernel.

HLAT specifications and functional descriptions are included in the Intel

Architecture

Instruction Set Extensions Programming Reference. Available at:

https://software.intel.com/en-us/download/intel-architecture-instruction-set-

extensions-programming-reference

Security Technologies

Intel

Trusted Execution Technology

Intel

Trusted Execution Technology (Intel

TXT) defines platform-level

enhancements that provide the building blocks for creating trusted platforms.

The Intel

TXT platform helps to provide the authenticity of the controlling

environment such that those wishing to rely on the platform can make an appropriate

trust decision. The Intel

TXT platform determines the identity of the controlling

environment by accurately measuring and verifying the controlling software.

Another aspect of the trust decision is the ability of the platform to resist attempts to

change the controlling environment. The Intel

TXT platform will resist attempts by

software processes to change the controlling environment or bypass the bounds set by

the controlling environment.

Intel

TXT is a set of extensions designed to provide a measured and controlled

launch of system software that will then establish a protected environment for itself

and any additional software that it may execute.

These extensions enhance two areas:

• The launching of the Measured Launched Environment (MLE).

• The protection of the MLE from potential corruption.

The enhanced platform provides these launch and control interfaces using Safer Mode

Extensions (SMX).

The SMX interface includes the following functions:

• Measured/Verified launch of the MLE.

• Mechanisms to ensure the above measurement is protected and stored in a secure

location.

• Protection mechanisms that allow the MLE to control attempts to modify itself.

The processor also offers additional enhancements to System Management Mode

(SMM) architecture for enhanced security and performance. The processor provides

new MSRs to:

• Enable a second SMM range

2.3

2.3.1

Technologies—Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

May 2025 Datasheet, Volume 1 of 2

Doc. No.: 743844, Rev.: 015 39

• Enable SMM code execution range checking

• Select whether SMM Save State is to be written to legacy SMRAM or to MSRs

• Determine if a thread is going to be delayed entering SMM

• Determine if a thread is blocked from entering SMM

• Targeted SMI, enable/disable threads from responding to SMIs, both VLWs, and

IPI

For the above features, BIOS should test the associated capability bit before

attempting to access any of the above registers. The capability bits are discussed in

the register description.

For more information, refer to the Intel

Trusted Execution Technology Measured

Launched Environment Programming Guide at:

http://www.intel.com/content/www/us/en/software-developers/intel-txt-software-

development-guide.html.

NOTE

Intel

TXT Technology may not be available on all SKUs.

Intel

Advanced Encryption Standard New Instructions

The processor supports Intel

Advanced Encryption Standard New Instructions (Intel

AES-NI) that are a set of Single Instruction Multiple Data (SIMD) instructions that

enable fast and secure data encryption and decryption based on the Advanced

Encryption Standard (AES). Intel

AES-NI is valuable for a wide range of

cryptographic applications, such as applications that perform bulk encryption/

decryption, authentication, random number generation, and authenticated encryption.

AES is broadly accepted as the standard for both government and industrial

applications and is widely deployed in various protocols.

Intel

AES-NI consists of six Intel

SSE instructions. Four instructions, AESENC,

AESENCLAST, AESDEC, and AESDELAST facilitate high-performance AES encryption

and decryption. The other two, AESIMC and AESKEYGENASSIST, support the AES key

expansion procedure. Together, these instructions provide full hardware for supporting

AES; offering security, high performance, and a great deal of flexibility.

This generation of the processor has increased the performance of the Intel

AES-NI

significantly compared to previous products.

The Intel

AES-NI specifications and functional descriptions are included in the Intel

64 Architectures Software Developer’s Manual, Volume 2. Available at:

http://www.intel.com/products/processor/manuals

NOTE

Intel

AES-NI Technology may not be available on all SKUs.

2.3.2

Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors—Technologies

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

Datasheet, Volume 1 of 2 May 2025

40 Doc. No.: 743844, Rev.: 015