743844-015.pdf - 第137页

USB-C Sub-system xHCI/xDCI Controllers The processor supports xHCI/xDCI controllers. The native USB 3 path proceeds from the memory directly to PHY . USB 3 Controllers Extensible Host Controller Interface (xHCI) Extensib…

USB4 architecture (formerly known as Thunderbolt 3 protocol) is a transformational

high-speed, dual protocol I/O, and it provides flexibility and simplicity by

encapsulating both data (PCIe* & USB3) and video

(DisplayPort*) on a single cable connection that can daisy-chain up to six devices.

USB4/Thunderbolt controllers act as a point of entry or a point of exit in the USB4

domain. The USB4 domain is built as a daisy chain of USB4/Thunderbolt enabled

products for the encapsulated protocols - PCIe, USB3 and DisplayPort. These protocols

are encapsulated into the USB4 fabric and can be tunneled across the domain.

USB4 controllers can be implemented in various systems such as PCs, laptops and

tablets, or devices such as storage, docks, displays, home entertainment, cameras,

computer peripherals, high end video editing systems, and any other PCIe based

device that can be used to extend system capabilities outside of the system's box.

The integrated connection maximum data rate is 20.625 Gbps per lane but supports

also 20.0 Gbps, 10.3125 Gbps, and 10.0 Gbps and is compatible with older

Thunderbolt

™

device speeds.

USB 4 Host Router Implementation Capabilities

The integrated USB-C sub-system implements the following interfaces via USB 4:

• Up to two DisplayPort* sink interfaces each one capable of:

— DisplayPort 1.4 specification for tunneling

— 1.62 Gbps or 2.7 Gbps or 5.4 Gbps or 8.1 Gbps link rates

— x1, x2 or x4 lane operation

— Support for DSC compression

• Up to two PCI Express* Root Port interfaces each one capable of:

— PCI Express* 3.0 x4 compliant @ 8.0 GT/s

• Up to two xHCI Port interfaces each one capable of:

— USB 3.2 Gen2x1 (10 Gbps)

• USB 4 Host Interface:

— PCI Express* 3.0 x4 compliant endpoint

— Supports simultaneous transmit and receive on 12 paths

— Raw mode and frame mode operation configurable on a per-path basis

— MSI and MSI-X support

— Interrupt moderation support

• USB 4 Time Management Unit (TMU):

• Up to two Interfaces to USB-C* connectors, each one supports:

— USB4 PD entry mode, as well as TBT 3 compatibility mode, each supporting:

• 20 paths per port

• Each port support 20.625/20.0 Gbps or 10.3125/10.0 Gbps link rates.

• 16 counters per port

6.2.1

Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors—USB-C* Sub System

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

Datasheet, Volume 1 of 2 May 2025

136 Doc. No.: 743844, Rev.: 015

USB-C Sub-system xHCI/xDCI Controllers

The processor supports xHCI/xDCI controllers. The native USB 3 path proceeds from

the memory directly to PHY.

USB 3 Controllers

Extensible Host Controller Interface (xHCI)

Extensible Host Controller Interface (xHCI) is an interface specification that defines

Host Controller for a universal Serial Bus (USB 3), which is capable of interfacing with

USB 1.x, 2.0, and 3.x compatible devices.

In case that a device (example, USB3 mouse) was connected to the computer, the

computer will work as Host and the xHCI will be activated inside the CPU.

The xHCI controller support link rate of up to USB 3.2 Gen 2x2 (2x10G).

Extensible Device Controller Interface (xDCI)

Extensible Device Controller Interface (xDCI) is an interface specification that defines

Device Controller for a universal Serial Bus (USB 3), which is capable of interfacing

with USB 1.x, 2.0, and 3.x compatible devices.

In case that the computer is connected as a device (example, tablet connected to

desktop) to another computer then the xDCI controller will be activated inside the

device and will talk to the Host at the other computer.

The xDCI controller support link rate of up to USB 3.2 Gen 1x1 (5G).

NOTE

These controllers are instantiated in the processor die as a separate PCI function

functionality for the USB-C* capable ports.

USB-C Sub-System PCIe Interface

Table 49. PCIe via USB4 Configuration

USB4 IPs USB4_PCIe

P/H/U/U Refresh Processor Line

USB-C* Ports

USB4_DMA0

USB4_PCIE0 TCP0

USB4_PCIE1 TCP1

USB4_DMA1

USB4_PCIE2 TCP2

USB4_PCIE3 TCP3

6.3

6.3.1

6.3.2

USB-C* Sub System—Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

May 2025 Datasheet, Volume 1 of 2

Doc. No.: 743844, Rev.: 015 137

Table 50. PCIe via USB4 Configuration

USB4 IPs USB4_PCIe PX Processor Line USB-C* Ports

USB4_DMA0

USB4_PCIE0 TCP0

USB4_PCIE1 TCP1

USB4_DMA1

USB4_PCIE2 TCP2

USB4_PCIE3 N/A

USB-C Sub-System Display Interface

Refer Display on page 153.

6.4

Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors—USB-C* Sub System

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

Datasheet, Volume 1 of 2 May 2025

138 Doc. No.: 743844, Rev.: 015