743844-015.pdf - 第58页

Figure 13. Telemetry Aggregator Clock Topology The processor has 3 reference clocks that drive the v arious components within the SoC: • Processor reference clock or base clock (BCLK). 100MHz with SSC. • PCIe reference c…

An update to the Linux* performance utility, with support for Intel

PT, is available for

download at https://github.com/virtuoso/linux-perf/tree/intel_pt. It requires

rebuilding the kernel and the perf utility.

Platform CrashLog

• The CrashLog feature is intended for use by system builders (OEMs) as a means to

triage and perform first level debug of failures.

• CrashLog enables the BIOS or the OS to collect data on failures with the intent to

collect and classify the data as well as analyze failure trends.

• CrashLog is a mechanism to collect debug information into a single location and

then allow access to that data via multiple methods, including the BIOS and OS of

the failing system.

• CrashLog is initiated by a Crash Data Detector on observation of error conditions

(TCO watchdog timeout, machine check exceptions, etc.).

• Crash Data Detector notifies the Crash Data Requester of the error condition in

order for the Crash Data Requester to collect Crash Data from several different IPs

and/or Crash Nodes and stores the data to the Crash Data Storage (on-die SRAM)

prior to the reset.

• After the system has rebooted, the Crash Data Collector reads the Crash Data

from the Crash Data Storage and makes the data available to either to software

and/or back to a central server to track error frequency and trends.

Telemetry Aggregator

The Telemetry Aggregator serves as an architectural and discoverable interface to

hardware telemetry:

• Standardized PCIe discovery solution that enables software to discover and

manage telemetry across products

• Standardized definitions for telemetry decode, including data type definitions

• Exposure of commonly used telemetry for power and performance debug

including:

— P-State status, residency and counters

— C-State status, residency and counters

— Energy monitoring

— Device state monitoring (for example, PCIe L1)

— Interconnect/bus bandwidth counters

— Thermal monitoring

Exposure of SoC state snapshot for atomic monitoring of package power states,

uninterrupted by software that reads.

The Telemetry Aggregator is also a companion to the CrashLog feature where data is

captured about the SoC at the point of a crash. These counters can provide insights

into the nature of the crash.

2.6.2

2.6.3

Technologies—Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

May 2025 Datasheet, Volume 1 of 2

Doc. No.: 743844, Rev.: 015 57

Figure 13. Telemetry Aggregator

Clock Topology

The processor has 3 reference clocks that drive the various components within the

SoC:

• Processor reference clock or base clock (BCLK). 100MHz with SSC.

• PCIe reference clock (PCTGLK). 100MHz with SSC.

• Fixed clock. 38.4MHz without SSC (crystal clock).

BCLK drives the following clock domains:

• Core

• Ring

• Graphics (GT)

• Memory Controller (MC)

• System Agent (SA)

PCTGLK drives the following clock domains:

• PCIe Controller(s)

• DMI/OPIO

Fixed clock drives the following clock domains:

• Display

• SVID controller

• Time Stamp Counters (TSC)

• Type C subsystem

2.7

Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors—Technologies

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

Datasheet, Volume 1 of 2 May 2025

58 Doc. No.: 743844, Rev.: 015

Integrated Reference Clock PLL

The processor includes a phase lock loop (PLL) that generates the reference clock for

the processor from a fixed crystal clock. The processor reference clock is also referred

to as Base Clock or BCLK.

By integrating the BCLK PLL into the processor die, a cleaner clock is achieved at a

lower power compared to the legacy PCH BCLK PLL solution.

The BCLK PLL has controls for RFI/EMI mitigations as well as Overclocking capabilities.

Intel Volume Management Device Technology

Objective

Standard Operating Systems generally recognize individual PCIe Devices and load

individual drivers. This is undesirable in some cases such as, for example, when there

are several PCIe-based hard-drives connected to a platform where the user wishes to

configure them as part of a RAID array. The Operating System current treats

individual hard-drives as separate volumes and not part of a single volume.

In other words, the Operating System requires multiple PCIe devices to have multiple

driver instances, making volume management across multiple host bus adapters

(HBAs) and driver instances difficult.

Intel Volume Management Device (VMD) technology provides a means to provide

volume management across separate PCI Express HBAs and SSDs without requiring

operating system support or communication between drivers. For example, the OS will

see a single RAID volume instead of multiple storage volumes, when Volume

Management Device is used.

Overview

Intel Volume Management Device technology does this by obscuring each storage

controller from the OS, while allowing a single driver to be loaded that would control

each storage controller.

Intel Volume Management technology requires support in BIOS and driver, memory

and configuration space management.

2.7.1

2.8

Technologies—Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

May 2025 Datasheet, Volume 1 of 2

Doc. No.: 743844, Rev.: 015 59