743844-015.pdf - 第122页

DDR Frequency Shifting DDR interfaces emit electromagnetic radiation which can couple to the antennas of various r adios that are integrated in the system, and cause r adio frequency interference (RFI). The DDR Radio Fre…

Processor Technology

DDR

Maximum

Rate

[MT/s]

SAGV-LowBW SAGV-MedBW SAGV-HighBW

SAGV-

MaxBW/

lowest latency

DDR5 1DPC on

2DPC UDIMM S

only

4400 2000 G2 3600 G2 4000 G2 4400 G2

DDR5 1DPC on

2DPC SODIMM

(HX only)

4000 2000 G2 3600 G2 3600 G2 4000 G2

Processor

4,5

Refresh

DDR5 1DPC on

2DPC 1R

SODIMMHX

Refresh only

4400 2000 G2 3600 G2 4000 G2 4400 G2

DDR5

6,7

2DPC

1R/1R HX Refresh

only

4400 2000 G2 3600 G2 4000 G2 4400 G2

DDR5

6,7

2DPC

2R/2R HX Refresh

only

4000 2000 G2 3600 G2 3600 G2 4000 G2

Processor

4,5

S/S refresh/HX

DDR5

2DPC

1R/1R

4000 2000 G2 3600 G2 3600 G2 4000 G2

DDR5

2DPC

2R/2R

3600 2000 G2 3200 G2 3200 G2 3600 G2

Processor

H/P/U/U-

Refresh /H-

Refresh

LPDDR4x 4266 2666 G4 3733 G4 4266G4 4266 G2

LPDDR5/x 1R PCB

6400 2400 G4 6000 G4 6400 G4 5200 G2

LPDDR5/x 2R PCB

T4 Refresh only

6400 2400 G4 6000 G4 6400 G4 5200 G2

LPDDR5/x 2R PCB

6000 2400 G4 5600 G4 6000 G4 5200 G2

LPDDR5 2R PCB

4800 2400 G4 4400 G4 4800 G4 4800 G2

LPDDR5 1R PCB

T3 LPDDR5x

1R/2R PCB T3

5200 2400 G4 4400 G4 5200 G4 4800 G2

DDR4 3200 2133 G2 2933 G2 3200 G2 2666 G1

DDR5 5600 2000 G2 3600 G2 5200 G2 5600 G2

DDR5 5200 2000 G2 3600 G2 4800 G2 5200 G2

Notes: 1. The Processor supports dynamic gearing technology where the Memory Controller can run at 1:1 (Gear-1,

Legacy mode) or 1:2 (Gear-2 mode) and 1:4 (Gear-4 mode) ratio of DRAM speed. The gear ratio is the ratio of

DRAM speed to Memory Controller Clock.

MC Channel Width equal to DDR Channel width multiply by Gear Ratio

2. SA-GV modes

a. LowBW- Low frequency point, Minimum Power point. Characterized by low power, low BW, high latency. The

system will stay at this point during low to moderate BW consumption.

b. MedBW - Tuned for balance between power & performance.

c. HighBW Characterized by high power, low latency, moderate BW also used as RFI mitigation point.

d. MaxBW/ lowest latency Lowest Latency point, low BW and highest power.

3. Intel

System Agent Enhanced Speed Step

is not enabled for S/S Refresh-Processor 125W/150W SKUs

4. SAGV point may change based on memory module Type.

5. On mixed module type configurations, the selected SAGV point will be the set to the lower frequency

configuration.

Memory—Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

May 2025 Datasheet, Volume 1 of 2

Doc. No.: 743844, Rev.: 015 121

DDR Frequency Shifting

DDR interfaces emit electromagnetic radiation which can couple to the antennas of

various radios that are integrated in the system, and cause radio frequency

interference (RFI).

The DDR Radio Frequency Interference Mitigation (DDR RFIM) feature is primarily

aimed at resolving narrowband RFI from DDR4/5 and LPDDR4/5 technologies for the

Wi-Fi* high and ultra-high bands (~5-7 GHz) .

By changing the DDR data rate, the harmonics of the clock can be shifted out of a

radio band of interest, thus mitigating RFI to that radio. This feature is working with

SAGV on, the 3

SAGV point is used as RFI mitigation point.

Memory Controller (MC)

The integrated memory controller is responsible for transferring data between the

processor and the DRAM as well as the DRAM maintenance. There are two instances of

MC, one per memory slice. Each controller is capable of supporting up to four channels

of LPDDR4x and LPDDR5, two channels of DDR5 and one channel of DDR4.

The two controllers are independent and have no means of communicating with each

other, they need to be configured separately.

In a symmetric memory population, each controller only view half of the total physical

memory address space.

Both MC support only one technology in a system, DDR4 or DDR5 or LPDDR4X, or

LPDDR5. Mix of technologies in one system is not allowed.

Memory Controller Power Gate

Memory Controller Power Gating can only be done for MC0 which is connected to a

separate power domain. MC0 will be gated automatically when it is not occupied.

NOTE

MC1 cannot be gated.

System Memory Controller Organization Mode (DDR4/5 Only)

The IMC supports two memory organization modes, single-channel and dual-channel.

Depending upon how the DDR Schema and DIMM Modules are populated in each

memory channel, a number of different configurations can exist.

Single-Channel Mode

In this mode, all memory cycles are directed to a single channel. Single-Channel mode

is used when either the Channel A or Channel B DIMM connectors are populated in any

order, but not both.

Dual-Channel Mode – Intel

Flex Memory Technology Mode

The IMC supports Intel Flex Memory Technology Mode. Memory is divided into a

symmetric and asymmetric zone. The symmetric zone starts at the lowest address in

each channel and is contiguous until the asymmetric zone begins or until the top

5.1.3.3

5.1.4

5.1.5

5.1.6

Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors—Memory

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

Datasheet, Volume 1 of 2 May 2025

122 Doc. No.: 743844, Rev.: 015

address of the channel with the smaller capacity is reached. In this mode, the system

runs with one zone of dual-channel mode and one zone of single-channel mode,

simultaneously, across the whole memory array.

NOTE

Channels A and B can be mapped for physical channel 0 and 1 respectively or vice

versa; however, channel A size should be greater or equal to channel B size.

Figure 19. Intel

DDR4/5 Flex Memory Technology Operations

MC BMC A

B B

Non interleaved

access

Dual channel

interleaved access

TOM

MC A and MC B can be configured to be physical channels 0 or 1

B – The largest physical memory amount of the smaller size memory module

C – The remaining physical memory amount of the larger size memory module

Dual-Channel Symmetric Mode (Interleaved Mode)

Dual-Channel Symmetric mode, also known as interleaved mode, provides maximum

performance on real world applications. Addresses are ping-ponged between the

channels after each cache line (64-byte boundary). If there are two requests, and the

second request is to an address on the opposite channel from the first, that request

can be sent before data from the first request has returned. If two consecutive cache

lines are requested, both may be retrieved simultaneously, since they are ensured to

be on opposite channels. Use Dual-Channel Symmetric mode when both Channel A

and Channel B DIMM connectors are populated in any order, with the total amount of

memory in each channel being the same.

Memory—Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

May 2025 Datasheet, Volume 1 of 2

Doc. No.: 743844, Rev.: 015 123