743844-015.pdf - 第121页

Processor Technology DDR Maximum Rate [MT/s] SAGV-LowBW SAGV-MedBW SAGV-HighBW SAGV- MaxBW/ lowest latency DDR5 1DPC on 2DPC UDIMM S only 4400 2000 G2 3600 G2 4000 G2 4400 G2 DDR5 1DPC on 2DPC SODIMM (HX only) 4000 2000 …

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System Memory Timing Support
Table 41. DDR System Memory Timing Support
DRAM
Device
Transfer
Rate
(MT/s)
tCL (tCK) tRCD (ns) tRP (ns) CWL (tCK) DPC
CMD
Mode
DDR4 3200 22 13.75 13.75
9-12,
14,16,18,20
1,2 2N
DDR5
4000 36 17 17.00 34 1 2N
4400 40 16.82 16.82 38 1,2
1
2N
4800 42 16.67 16.67 40 1 2N
5200 46 16.153 16.153 44 1 2N
5600 50 16.42 16.42 48 1 2N
Note:
1. 2 DPC supported when one slot is populated in each channel
Table 42. LPDDR System Memory Timing Support
DRAM
Device
Transfer Rate
(MT/s)
tCL (tCK) tRCD (ns) tRPpb (ns) tRPab (ns)
WL (tCK)
Set B
LPDDR4x 4266 36 18 18 21 34
LPDDR5/x
4800 13 18.33 18.33 21.67 12
5200 15 18.46 18.46 21.54 14
6000 16 18.72 18.46 21.28 15
6400 17 18.75 18.75 21.25 16
SAGV Points
SAGV (System Agent Geyserville) is a way by which they SoC can dynamically scale
the work point (V/F), by applying DVFS (Dynamic Voltage Frequency Scaling) based
on memory bandwidth utilization and/or the latency requirement of the various
workloads for better energy efficiency at System-Agent.heuristics are in charge of
providing request for work points by periodically evaluating the utilization of the
memory and IA stalls.
Table 43. SA Speed Enhanced Speed Steps (SA-GV) and Gear Mode Frequencies
Processor Technology
DDR
Maximum
Rate
[MT/s]
SAGV-LowBW SAGV-MedBW SAGV-HighBW
SAGV-
MaxBW/
lowest latency
Processor
4,5
S/S refresh/HX
DDR4 3200 2133 G2 2666 G1 2933 G1 3200 G1
DDR5 1DPC 2R
UDIMM / SODIMM
5200 2000 G2 3600 G2 4800 G2 5200 G2
DDR5 1DPC 1R
UDIMM /SODIMM
5600 2000 G2 3600 G2 5200 G2 5600 G2
DDR5 1DPC 2R
UDIMM S-Refresh
only
7
5600 2000 G2 3600 G2 5200 G2 5600 G2
continued...
5.1.3.1
5.1.3.2
R
Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors—Memory
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
Datasheet, Volume 1 of 2 May 2025
120 Doc. No.: 743844, Rev.: 015
Processor Technology
DDR
Maximum
Rate
[MT/s]
SAGV-LowBW SAGV-MedBW SAGV-HighBW
SAGV-
MaxBW/
lowest latency
DDR5 1DPC on
2DPC UDIMM S
only
4400 2000 G2 3600 G2 4000 G2 4400 G2
DDR5 1DPC on
2DPC SODIMM
(HX only)
4000 2000 G2 3600 G2 3600 G2 4000 G2
Processor
4,5
HX
Refresh
DDR5 1DPC on
2DPC 1R
SODIMMHX
Refresh only
7
4400 2000 G2 3600 G2 4000 G2 4400 G2
DDR5
6,7
2DPC
1R/1R HX Refresh
only
4400 2000 G2 3600 G2 4000 G2 4400 G2
DDR5
6,7
2DPC
2R/2R HX Refresh
only
4000 2000 G2 3600 G2 3600 G2 4000 G2
Processor
4,5
S/S refresh/HX
DDR5
6
2DPC
1R/1R
4000 2000 G2 3600 G2 3600 G2 4000 G2
DDR5
6
2DPC
2R/2R
3600 2000 G2 3200 G2 3200 G2 3600 G2
Processor
5
H/P/U/U-
Refresh /H-
Refresh
LPDDR4x 4266 2666 G4 3733 G4 4266G4 4266 G2
LPDDR5/x 1R PCB
T4
6400 2400 G4 6000 G4 6400 G4 5200 G2
LPDDR5/x 2R PCB
T4 Refresh only
7
6400 2400 G4 6000 G4 6400 G4 5200 G2
LPDDR5/x 2R PCB
T4
6000 2400 G4 5600 G4 6000 G4 5200 G2
LPDDR5 2R PCB
T3
4800 2400 G4 4400 G4 4800 G4 4800 G2
LPDDR5 1R PCB
T3 LPDDR5x
1R/2R PCB T3
5200 2400 G4 4400 G4 5200 G4 4800 G2
DDR4 3200 2133 G2 2933 G2 3200 G2 2666 G1
DDR5 5600 2000 G2 3600 G2 5200 G2 5600 G2
DDR5 5200 2000 G2 3600 G2 4800 G2 5200 G2
Notes: 1. The Processor supports dynamic gearing technology where the Memory Controller can run at 1:1 (Gear-1,
Legacy mode) or 1:2 (Gear-2 mode) and 1:4 (Gear-4 mode) ratio of DRAM speed. The gear ratio is the ratio of
DRAM speed to Memory Controller Clock.
MC Channel Width equal to DDR Channel width multiply by Gear Ratio
2. SA-GV modes
a. LowBW- Low frequency point, Minimum Power point. Characterized by low power, low BW, high latency. The
system will stay at this point during low to moderate BW consumption.
b. MedBW - Tuned for balance between power & performance.
c. HighBW Characterized by high power, low latency, moderate BW also used as RFI mitigation point.
d. MaxBW/ lowest latency Lowest Latency point, low BW and highest power.
3. Intel
®
System Agent Enhanced Speed Step
®
is not enabled for S/S Refresh-Processor 125W/150W SKUs
4. SAGV point may change based on memory module Type.
5. On mixed module type configurations, the selected SAGV point will be the set to the lower frequency
configuration.
R
Memory—Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
May 2025 Datasheet, Volume 1 of 2
Doc. No.: 743844, Rev.: 015 121
DDR Frequency Shifting
DDR interfaces emit electromagnetic radiation which can couple to the antennas of
various radios that are integrated in the system, and cause radio frequency
interference (RFI).
The DDR Radio Frequency Interference Mitigation (DDR RFIM) feature is primarily
aimed at resolving narrowband RFI from DDR4/5 and LPDDR4/5 technologies for the
Wi-Fi* high and ultra-high bands (~5-7 GHz) .
By changing the DDR data rate, the harmonics of the clock can be shifted out of a
radio band of interest, thus mitigating RFI to that radio. This feature is working with
SAGV on, the 3
rd
SAGV point is used as RFI mitigation point.
Memory Controller (MC)
The integrated memory controller is responsible for transferring data between the
processor and the DRAM as well as the DRAM maintenance. There are two instances of
MC, one per memory slice. Each controller is capable of supporting up to four channels
of LPDDR4x and LPDDR5, two channels of DDR5 and one channel of DDR4.
The two controllers are independent and have no means of communicating with each
other, they need to be configured separately.
In a symmetric memory population, each controller only view half of the total physical
memory address space.
Both MC support only one technology in a system, DDR4 or DDR5 or LPDDR4X, or
LPDDR5. Mix of technologies in one system is not allowed.
Memory Controller Power Gate
Memory Controller Power Gating can only be done for MC0 which is connected to a
separate power domain. MC0 will be gated automatically when it is not occupied.
NOTE
MC1 cannot be gated.
System Memory Controller Organization Mode (DDR4/5 Only)
The IMC supports two memory organization modes, single-channel and dual-channel.
Depending upon how the DDR Schema and DIMM Modules are populated in each
memory channel, a number of different configurations can exist.
Single-Channel Mode
In this mode, all memory cycles are directed to a single channel. Single-Channel mode
is used when either the Channel A or Channel B DIMM connectors are populated in any
order, but not both.
Dual-Channel Mode – Intel
®
Flex Memory Technology Mode
The IMC supports Intel Flex Memory Technology Mode. Memory is divided into a
symmetric and asymmetric zone. The symmetric zone starts at the lowest address in
each channel and is contiguous until the asymmetric zone begins or until the top
5.1.3.3
5.1.4
5.1.5
5.1.6
R
Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors—Memory
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
Datasheet, Volume 1 of 2 May 2025
122 Doc. No.: 743844, Rev.: 015