743844-015.pdf - 第68页

— For package C -states, the processor is not required to enter C0 before entering any other C -state. — Entry into a package C-state ma y be subject to auto-demotion – that is, the processor may keep the package in a de…

Table 7. Core C-states

Core C-

State

C-State Request

Instruction

Description

C0 N/A

The normal operating state of a processor IA core where a code is being

executed

C1 MWAIT(C1)

AutoHalt - core execution stopped, autonomous clock gating (package in

C0 state)

C1E MWAIT(C1E)

Core C1 + lowest frequency and voltage operating point (package in C0

state)

C6-C10

MWAIT(C6/C8/10)

or IO

read=P_LVL3//6/8

Processor IA, flush their L1 instruction cache, the L1 data cache, and L2

cache to the LLC shared cache cores save their architectural state to an

SRAM before reducing IA cores voltage, if possible may also be reduced to

0V. Core clocks are off.

Core C-State Auto-Demotion

In general, deeper C-states, such as C6, have long latencies and have higher energy

entry/exit costs. The resulting performance and energy penalties become significant

when the entry/exit frequency of a deeper C-state is high. Therefore, incorrect or

inefficient usage of deeper C-states have a negative impact on battery life and idle

power. To increase residency and improve battery life and idle power in deeper C-

states, the processor supports C-state auto-demotion.

C-State auto-demotion:

• C6 to C1/C1E

The decision to demote a processor IA core from C6 to C1/C1E is based on each

processor IA core’s immediate residency history. Upon each processor IA core C6

request, the processor IA core C-state is demoted to C1 until a sufficient amount of

residency has been established. At that point, a processor IA core is allowed to go into

C6 . If the interrupt rate experienced on a processor IA core is high and the processor

IA core is rarely in a deep C-state between such interrupts, the processor IA core can

be demoted to a C1 state.

This feature is disabled by default. BIOS should enable it in the

PMG_CST_CONFIG_CONTROL register. The auto-demotion policy is also configured by

this register.

Package C-States

The processor supports C0, C2, C3, C6, C8, and C10 package states. The following is a

summary of the general rules for package C-state entry. These apply to all package C-

states, unless specified otherwise:

• A package C-state request is determined by the lowest numerical processor IA

core C-state amongst all processor IA cores.

• A package C-state is automatically resolved by the processor depending on the

processor IA core idle power states and the status of the platform components.

— Each processor IA core can be at a lower idle power state than the package if

the platform does not grant the processor permission to enter a requested

package C-state.

— The platform may allow additional power savings to be realized in the

processor.

3.2.5

Power Management—Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

May 2025 Datasheet, Volume 1 of 2

Doc. No.: 743844, Rev.: 015 67

— For package C-states, the processor is not required to enter C0 before

entering any other C-state.

— Entry into a package C-state may be subject to auto-demotion – that is, the

processor may keep the package in a deeper package C-state then requested

by the operating system if the processor determines, using heuristics, that the

deeper C-state results in better power/performance.

The processor exits a package C-state when a break event is detected. Depending on

the type of break event, the processor does the following:

• If a processor IA core break event is received, the target processor IA core is

activated and the break event message is forwarded to the target processor IA

core.

— If the break event is not masked, the target processor IA core enters the

processor IA core C0 state and the processor enters package C0.

— If the break event is masked, the processor attempts to re-enter its previous

package state.

• If the break event was due to a memory access or snoop request,

— But the platform did not request to keep the processor in a higher package C-

state, the package returns to its previous C-state.

— And the platform requests a higher power C-state, the memory access or

snoop request is serviced and the package remains in the higher power C-

state.

Figure 16. Package C-State Entry and Exit

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Package C0

Package c2

Package C6 Package C8 Package C10Package C3*

PKG C2 and C3 can not be requested explicitly by the software

Table 8. Package C-States

Package

C state

Description Dependencies

PKG C0

Processor active state.

At least one IA core in C0.

continued...

Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors—Power Management

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

Datasheet, Volume 1 of 2 May 2025

68 Doc. No.: 743844, Rev.: 015

Package

C state

Description Dependencies

Processor Graphic in RC0 (Graphics active state) or RC6 (Graphics Core power

down state).

PKG C2

Cannot be requested explicitly by the Software.

All processor IA cores in C6 or deeper + Processor Graphic cores in RC6,

memory path may be open.

The processor will enter Package C2 when:

• Transitioning from Package C0 to deep Package C state or from deep

Package C state to Package C0.

• All IA cores requested C6 or deeper + Processor Graphic cores in RC6 but

there are constraints (LTR, programmed timer events in the near future

and so forth) prevent entry to any state deeper than C2 state.

• All IA cores requested C6 or deeper + Processor Graphic cores in RC6 but

a device memory access request is received. Upon completion of all

outstanding memory requests, the processor transitions back into a

deeper package C-state.

All processor IA cores in C6 or

deeper.

Processor Graphic cores in RC6.

PKG C3

Cannot be requested explicitly by the Software.

All cores in C6 or deeper + Processor Graphics in RC6, LLC may be flushed

and turned off, memory in self refresh, memory clock stopped.

The processor will enter Package C3 when:

• All IA cores in C6 or deeper + Processor Graphic cores in RC6.

• The platform components/devices allows proper LTR for entering Package

C3.

All processor IA cores in C6 or

deeper.

Processor Graphics in RC6.

memory in self refresh, memory

clock stopped.

LLC may be flushed and turned off.

PKG C6

Package C3 + BCLK is off + IMVP9.1 VRs voltage reduction/PSx state is

possible.

The processor will enter Package C6 when:

• All IA cores in C6 or deeper + Processor Graphic cores in RC6.

• The platform components/devices allow proper LTR for entering Package

C6.

Package C3.

BCLK is off.

IMVP9.1 VRs voltage

reduction/PSx state is possible.

PKG C8

Of all IA cores requested C8 + LLC should be flushed at once, voltage will be

removed from the LLC.

The processor will enter Package C8 when:

• All IA cores in C8 or deeper + Processor Graphic cores in RC6.

• The platform components/devices allow proper LTR for entering Package

C8.

Package C6

If all IA cores requested C8, LLC is

flushed in a

single step, voltage will be

removed from the LLC.

PKG

C10

Package C8 + display in PSR or powered, all VRs at PS4 + crystal clock off.

The processor will enter Package C10 when:

• All IA cores in C10 + Processor Graphic cores in RC6.

• The platform components/devices allow proper LTR for entering Package

C10.

Package C8.

All IA cores in C8 or deeper.

Display in PSR or powered off

All VRs at PS4.

Crystal clock off.

Note: Display In PSR is only on single embedded panel configuration and panel support PSR feature.

Package C-State Auto-Demotion

The Processor may demote the Package C-State to a shallower Package C-State to

enable better performance, for example instead of going into Package C10, processor

will demote to Package C6 (and shallower as required).

The processor's decision to demote the Package C-State is based on Power

management parameters such as required C states latencies, entry/exit energy/power,

Core wake rates, and device LTR (Latency Tolerance Report). This means that the

processor is optimized to minimize platform energy for scenarios with low idle time.

Power Management—Intel

Core

™

, Xeon

™

6300 And Xeon

™

E 2400 Processors

Generation Intel

Core

™

, Intel

Core

™

Generation, Intel

Core

™

Processor (Series 1) and (Series 2), Intel

Xeon

™

2400 Processor and Intel

Xeon

™

6300 Processor

May 2025 Datasheet, Volume 1 of 2

Doc. No.: 743844, Rev.: 015 69