743844-015.pdf - 第208页

Symbol Parameter Minimum Typical Units Notes 1 DDR_VREF_CA VREF output voltage V DD2 /2 -100mV V DD2 /2 T rainable V DD2 /2 +100mV V 14,15 SM_RCOMP[0] Command COMP R esistance 99 100 101 Ω 8 SM_RCOMP[1] Data COMP R esist…

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Symbol Parameter Segment Minimum Typical Maximum Units Notes
1,2,5
Icc
MAX_1P8_PROC
Maximum
Current for
Vcc
1P8_PROC
S/S Refresh/E/E
Refresh -
Processor Line
— — 106 mA 4
Icc
MAX_1P8_PROC
Maximum
Current for
Vcc
1P8_PROC
HX/HX Refresh-
Processor Line — — 140 mA 4
Notes: 1. All specifications in this table are based on estimates and simulations or empirical data. These specifications will
be updated with characterized data from silicon measurements at a later date.
2. Long term reliability cannot be assured in conditions above or below Maximum/Minimum functional limits.
3. The voltage specification requirements are measured on capacitors pads near to the package, with an
oscilloscope set to 100 MHz bandwidth, 1.5 pF maximum probe capacitance, and 1 MΩ minimum impedance.
The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the
system is not coupled into the oscilloscope probe.
4. Vcc
1P8_PROC
power rail may be named in different document as Vcc
1P8_CPU
5. For S-process line, AC noise spec include VR self generated noise or input source AC noise that passes through
to VR output and droop/overshoot due to transient load.
Processor Interfaces DC Specifications
DDR4 DC Specifications
Table 86. DDR4 Signal Group DC Specifications
Symbol Parameter Minimum Typical Units Notes
1
V
IL
Input Low Voltage — 0.75*Vdd2 0.68*Vdd2 V 2, 3, 4
V
IH
Input High Voltage
0.82*Vdd2 0.75*Vdd2
—
Maximum
V 2, 3, 4
R
ON_UP(DQ)
Data Buffer pull-up Resistance 30 — 50 Ω 5,12
R
ON_DN(DQ)
Data Buffer pull-down Resistance 30 — 50
R
ODT(DQ)
On-die termination equivalent
resistance for data signals
40 — 200 Ω 6, 12
V
ODT(DC)
On-die termination DC working point
(driver set to receive mode)
0.45*Vdd2 — 0.85*Vdd2 V 12
R
ON_UP(CK)
Clock Buffer pull-up Resistance 25 — 45 Ω 5, 12
R
ON_DN(CK)
Clock Buffer pull-down Resistance 25 — 45 Ω 5, 12
R
ON_UP(CMD)
Command Buffer pull-up Resistance 25 — 45 Ω 5, 12
R
ON_DN(CMD)
Command Buffer pull-down Resistance 25 — 45 Ω 5, 12
R
ON_UP(CTL)
Control Buffer pull-up Resistance 25 — 45 Ω 5, 12
R
ON_DN(CTL)
Control Buffer pull-down Resistance 25 — 45 Ω 5, 12
R
ON_UP
(SM_PG_CNTL1)
System Memory Power Gate Control
Buffer Pull-up Resistance
45 — 125 Ω —
R
ON_DN
(SM_PG_CNTL1)
System Memory Power Gate Control
Buffer Pull- down Resistance
40 — 130 Ω —
I
LI
Input Leakage Current (DQ, CK)
0 V
0.2* V
DD2
0.8* V
DD2
— — 1.1 mA —
continued...
13.2.2
13.2.2.1
R
Electrical Specifications—Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
May 2025 Datasheet, Volume 1 of 2
Doc. No.: 743844, Rev.: 015 207
Symbol Parameter Minimum Typical Units Notes
1
DDR_VREF_CA VREF output voltage
V
DD2
/2
-100mV
V
DD2
/2
Trainable
V
DD2
/2
+100mV
V 14,15
SM_RCOMP[0] Command COMP Resistance 99 100 101 Ω 8
SM_RCOMP[1] Data COMP Resistance 99 100 101 Ω 8
SM_RCOMP[2] ODT COMP Resistance 99 100 101 Ω 8
Notes: 1. All specifications in this table apply to all processor frequencies. Timing specifications only depend on the
operating frequency of the memory channel and not the maximum rated frequency
2. V
IL
is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value.
3. V
IH
is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value.
4. V
IH
and V
OH
may experience excursions above V
DD2
. However, input signal drivers should comply with the signal
quality specifications.
5. Pull up/down resistance after compensation (assuming ±5% COMP inaccuracy). Note that BIOS power training
may change these values significantly based on margin/power trade-off. Refer to processor I/O Buffer Models
for I/V characteristics.
6. ODT values after COMP (assuming ±5% inaccuracy). BIOS MRC can reduce ODT strength towards
7. The minimum and maximum values for these signals are programmable by BIOS to one of the two sets.
8. SM_RCOMP[x] resistance should be provided on the system board with 1% resistors. SM_RCOMP[x] resistors
are to VSS. Values are pre-silicon estimations and are subject to change.
9. SM_DRAMPWROK must have a maximum of 15 ns rise or fall time over VDD2 * 0.30 ±100 mV and the edge
must be monotonic.
10.SM_VREF is defined as V
DD2
/2 for DDR4
11.R
ON
tolerance is preliminary and might be subject to change.
12.Maximum-minimum range is correct but center point is subject to change during MRC boot training.
13.Processor may be damaged if V
IH
exceeds the maximum voltage for extended periods.
14.AC peak noise of VREFCA will not be deviate by more than +/-1% of VDD (for reference +/-12mV).
15.+/-100mV if for frequency above 2400, 2400 and below the spec is +/-60mV.
DDR5 DC Specifications
Table 87. DDR5 Signal Group DC Specifications
Symbol Parameter Minimum Typical Maximum Units Notes
1
V
IL
Input Low Voltage 0.75*Vd
d2
0.65*Vdd2 V 2, 3, 4
V
IH
Input High Voltage
0.85*Vdd2
0.75*Vd
d2
- V 2, 3, 4
R
ON_UP(DQ)
Data Buffer pull-up Resistance 30 50 Ω 5,12
R
ON_DN(DQ)
Data Buffer pull-down Resistance 30 50
R
ODT(DQ)
On-die termination equivalent resistance for
data signals
30 240 Ω 6, 12
V
ODT(DC)
On-die termination DC working point (driver
set to receive mode)
0.4*Vdd2 Vddq V 12
R
ON_UP(CK)
Clock Buffer pull-up Resistance 30 50 Ω 5, 12
R
ON_DN(CK)
Clock Buffer pull-down Resistance 30 50 Ω 5, 12
R
ON_UP(CMD)
Command Buffer pull-up Resistance 30 50 Ω 5, 12
R
ON_DN(CMD)
Command Buffer pull-down Resistance 30 50 Ω 5, 12
R
ON_UP(CTL)
Control Buffer pull-up Resistance 30 50 Ω 5, 12
continued...
13.2.2.2
R
Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors—Electrical Specifications
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
Datasheet, Volume 1 of 2 May 2025
208 Doc. No.: 743844, Rev.: 015
Symbol Parameter Minimum Typical Maximum Units Notes
1
R
ON_DN(CTL)
Control Buffer pull-down Resistance 30 50 Ω 5, 12
R
ON_UP
(SM_PG_CNTL1)
System Memory Power Gate Control Buffer
Pull-up Resistance
Ω —
R
ON_DN
(SM_PG_CNTL1)
System Memory Power Gate Control Buffer
Pull- down Resistance
Ω —
I
LI
Input Leakage Current (DQ, CK)
0 V , 0.2* VDD2, 0.8* VDD2
0.2 mA —
DDR0_VREF_DQ
DDR1_VREF_DQ
VREF output voltage
NA NA NA V —
SM_RCOMP[0] Command COMP Resistance 99 100 101 Ω 8
SM_RCOMP[1] Data COMP Resistance 99 100 101 Ω 8
SM_RCOMP[2] ODT COMP Resistance 99 100 101 Ω 8
Notes: 1. All specifications in this table apply to all processor frequencies.Timing specifications only depend on the
operating frequency of the memory channel and not the maximum rated frequency
2. V
IL
is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value.
3. V
IH
is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value.
4. V
IH
and V
OH
may experience excursions above V
DD2
. However, input signal drivers should comply with the signal
quality specifications.
5. Pull up/down resistance after compensation (assuming ±5% COMP inaccuracy). Note that BIOS power training
may change these values significantly based on margin/power trade-off. Refer to processor I/O Buffer Models
for I/V characteristics.
6. ODT values after COMP (assuming ±5% inaccuracy). BIOS MRC can reduce ODT strength towards
7. The minimum and maximum values for these signals are programmable by BIOS to one of the two sets.
8. SM_RCOMP[x] resistance should be provided on the system board with 1% resistors. SM_RCOMP[x] resistors
are to VSS. Values are pre-silicon estimations and are subject to change.
9. SM_DRAMPWROK must have a maximum of 15 ns rise or fall time over VDD2 * 0.30 ±100 mV and the edge
must be monotonic.
10.SM_VREF is defined as V
DD2
/2 for DDR5
11.RON tolerance is preliminary and might be subject to change.
12.Maximum-minimum range is correct but center point is subject to change during MRC boot training.
13.Processor may be damaged if V
IH
exceeds the maximum voltage for extended periods.
LPDDR4x DC Specification
Table 88. LPDDR4x Signal Group DC Specifications
Symbol Parameter Minimum Typical Maximum Units Notes
1
V
IL
Input Low Voltage — 0.2*Vdd2 0.08*Vdd2 V 2, 3, 4
V
IH
0 = Input High Voltage 0.35*Vdd2 0.2*Vdd2 — V 2, 3, 4
R
ON_UP(DQ)
Data Buffer pull-up Resistance 30 — 50 Ω 5,12
R
ON_DN(DQ)
Data Buffer pull-down
Resistance
30 — 50 Ω 5,12
R
ODT(DQ)
On-die termination equivalent
resistance for data signals
40 — 200 Ω 6, 12
V
ODT(DC)
On-die termination DC working
point (driver set to receive
mode)
0.1*Vdd2 — 0.3*Vdd2 V 10
R
ON_UP(CK)
Clock Buffer pull-up Resistance 30 — 45 Ω 5, 12
continued...
13.2.2.3
R
Electrical Specifications—Intel
®
Core
™
, Xeon
™
6300 And Xeon
™
E 2400 Processors
13
th
Generation Intel
®
Core
™
, Intel
®
Core
™
14
th
Generation, Intel
®
Core
™
Processor (Series 1) and (Series 2), Intel
®
Xeon
™
E
2400 Processor and Intel
®
Xeon
™
6300 Processor
May 2025 Datasheet, Volume 1 of 2
Doc. No.: 743844, Rev.: 015 209