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SEMI E23-1104 © SEMI 1991, 2004 5 Figure 3A Cassette Load Seque nce (Wire- Connect ed Inte rface) Figure 3B Cassette Unload Sequence (Wire- Connect ed Inte rface) Figure 4A Cassette Load Seque nce (Photo-Coupled Interfac…

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SEMI E23-1104 © SEMI 1991, 2004 4
Table 3 Signals for the Photo-Coupled Parallel I/O Interface
Signal Type P/A
D
escription
VALID A->P This signal remains high (ON) while the data of CS_0, CS_1, CS_2 is effective.
(The data of CS_0, CS_1, CS_2 is not effective when VALID signal is OFF.)
CS_0 (LSB) CS_1 CS_2
(MSB)
A->P The 3-bit signals specify the cassette stage number (0 ~ 7) of the passive equip-
ment, to or from which the active equipment (robot vehicle) is going to transfer a
cassette. They are set before the VALID signal turns ON. VALID and
CS_0~CS_2 signal.
TR_REQ A->P This is the same in the wire-connected parallel I/O specification and is valid for
the specified CS.
L_REQ P->A This is the same in the wire-connected parallel I/O specification and is valid for
the specified CS.
U_REQ P->A This is the same in the wire-connected parallel I/O specification and is valid for
the specified CS.
READY P->A This is the same in the wire-connected parallel I/O specification and is valid for
the specified CS.
BUSY A->P This is the same in the wire-connected parallel I/O specification.
COMPT A->P This is the same in the wire-connected parallel I/O specification.
5.3.3 Cassette Transfer Sequence — Time charts for the cassette transfer sequence in the case of the photo-coupled
interface are shown in Figure 4 (a) and (b). After the active equipment (robot vehicle) reaches the process
equipment, it sets the CS_0, CS_1, CS_2 3-bit-signals to specify the CS number of the passive equipment, to or
from which the active equipment (robot vehicle) is going to transfer a cassette. Then the robot vehicle turns the
VALID signal ON, which shows the date of the CS_0, CS_1, CS_2 signal is effective. After the cassette stage is
specified, cassette transfer sequence is the same as in the wire-connected parallel I/O specification. TR_REQ,
L_REQ,U_REQ, READY signals show the data for the specified CS while the VALID signal is ON, and the CS_0,
CS_1, CS_2 signals are inhibited to change their data while the VALID signal is ON.
5.4 Error Detection and Recovery — The cassette transfer using this interface in the practical manufacturing lines
will need handshake time interval control, cassette misalignment detection, and report of alarm or error to find an
error or abnormal termination in the cassette transfer. An error recovery procedure with appropriate assist by human
operators will be also required. This standard, however, does not define the specifications related to the error
detection and recovery because of difference in process time, failure mode, and error recovery procedure of
individual equipment and system.
5.4.1 The recommendation for basic error detection is that the active equipment should control handshake time
intervals, and at least the interval time T between the beginning of the cassette transfer and the end of the transfer
should be controlled — see the time chart of the cassette transfer sequence shown in Figures 3(a), 3(b), 4(a), and
4(b), describing the time chart of the cassette transfer sequence.
SEMI E23-1104 © SEMI 1991, 2004 5
Figure 3A
Cassette Load Sequence
(Wire-Connected Interface)
Figure 3B
Cassette Unload Sequence
(Wire-Connected Interface)
Figure 4A
Cassette Load Sequence
(Photo-Coupled Interface)
Figure 4B
Cassette Load Sequence
(Photo-Coupled Interface)
SEMI E23-1104 © SEMI 1991, 2004 6
6 Connector and Interface Circuit
6.1 Wire-Connected Interface — One set of connectors
is provided for the CS’s that commonly input the
BUSY and COMPT signals.
6.1.1 Connector and Pin Assignment
1. Connector JIS-X-5103 (D-SUB type) ISO-4902
Every piece of equipment is to have female type
connectors.
2. Pin Assignment — The connector with 37 pins is
used. One connector is used for 1 to 4 cassette
stages and another connector is used for 5 to 7
cassette stages. The pin assignment is listed in
Tables 4a and 4b. Figure 5 shows the pin
assignment of the connector for 4 cassette stages.
Table 4 Pin Assignment for Wire-Connected Parallel
I/O Interface (Connector 2)
Pin No. Signal Pin No. Signal
1 CS1 L_REQ 20 CS1 L_REQ*
2 CS1 U_REQ 21 CS1 U_REQ*
3 CS1 READY 22 CS1 READY*
4 CS2 L_REQ 23 CS2 L_REQ*
5 CS2 U_REQ 24 CS2 U_REQ*
6 CS2 READY 25 CS2 READY*
7 CS3 L_REQ 26 CS3 L_REQ*
8 CS3 U_REQ 27 CS3 U_REQ*
9 CS3 READY 28 CS3 READY*
10 CS4 L_REQ 29 CS4 L_REQ*
11 CS4 U_REQ 30 CS4 U_REQ*
12 CS4 READY 31 CS4 READY*
13 CS1 TR_REQ 32 CS1 TR_REQ*
14 CS2 TR_REQ 33 CS2 TR_REQ*
15 CS3 TR_REQ 34 CS3 TR_REQ*
16 CS4 TR_REQ 35 CS4 TR_REQ*
17 COMPT 36 COMPT*
18 BUSY 37 BUSY*
19 38
*Vcc side (power source) for the current-driven type circuit. Common
side for the voltage-driven type circuit.
6.1.1.1 When one connector is used for only one
cassette stage, the connector with 15 pins may be used.
The pin assignment is listed in the Table 5.
6.1.2 Interface Circuit — The following two types of
interface circuits are used. (Interface circuit examples
are shown in Related Information 3.)
1. Voltage-driven Type Circuit — Driving voltage:
DC24 ± 2 V
2. Current-driven Type Circuit — Driving current: 10
mA ~ 20 mA
Figure 5
Pin Assignment for Wire-Connected Parallel I/O
Interface
Table 5 Pin Assignment for Wire-Connected
Parallel I/O Interface (Connector 1)
Pin No. Signal Pin No. Signal
1 CS5 L_REQ 20 CS5 L_REQ*
2 CS5 U_REQ 21 CS5 U_REQ*
3 CS5 READY 22 CS5 READY*
4 CS6 L_REQ 23 CS6 L_REQ*
5 CS6 U_REQ 24 CS6 U_REQ*
6 CS6 READY 25 CS6 READY*
7 CS7 L_REQ 26 CS7 L_REQ*
8 CS7 U_REQ 27 CS7 U_REQ*
9 CS7 READY 28 CS7 READY*
10 29
11 30
12 31
13 CS5 TR_REQ 32 CS5 TR_REQ*
14 CS6 TR_REQ 33 CS6 TR_REQ*
15 CS7 TR_REQ 34 CS7 TR_REQ*
16 35
17 36
18 37
19
*Vcc side (power source) for the current-driven type circuit. Common
side for the voltage-driven type circuit.