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SEMI G46-88 © SEMI 1988 3 Step 4 — T est each of th e sa mple devices and record the ∆ V F and CU dat a as shown in Figure 3. Step 5 — Select out the devices wi th the highest and lowest values of CU a nd put the remaini…
SEMI G46-88 © SEMI 1988 2
2.16 σ
∆
— the standard deviation if the ∆V
F
results for
a given test condition.
2.17 σ
CU
— the standard deviation o f the CU results
for a given test condition.
3 Test Operation
The following paragraphs describe in conceptual detail
the operation of the test for integrated circuit thermal
response.
3.1 Set-Up — Shown in Figure 1 i s the set-up required
for testing either active devices or thermal test chips.
Figure 1a is used for those cases in which the TSP is the
junction isolation diode forward biased voltage.
Thermal test chips and test IC’s for which the junction
isolation diode is either not available, or desirable for
temperature sensing, can be handled by the set-up
shown in Figure 1b.
3.2 Apparatus — To implement either version of
Figure 1 requires the following apparatus:
3.2.1 A constant voltage source capa ble of adjustment
to the desired value of V
H
and able to supply the I
H
value drawn by the DUT.
3.2.2 A constant current source to su pply I
M
with
sufficient voltage compliance to turn the TSP junction
fully on.
3.2.3 An electronic switch capable o f switching
between the heating period conditions and measurement
conditions in a time frame short enough to avoid DUT
cooling during the transition; this typically requires
switching in the microsecond range.
3.2.4 A voltage measurement circuit capable of
accurately making the V
H
measurement within the t
MD
(or t
MD
plus t
SW
, depending on the definitions stated
previously) time frame with millivolt resolution.
3.3 Operation and Waveforms — The test begins with
the adjustment of I
M
and V
H
to the desired values. Then
with the electronic switch in position 1, the value of V
F
is measured. The switch is then moved to position 2 for
a length of time equal to t
H
and the value of I
H
is
measured. Finally, at the conclusion of t
H
, the switch is
again moved to position 1 and the V
F
value is measured
within a time period defined by t
MD
(or t
MD
plus t
SW
,
depending on the definitions stated previously). The
voltage and current sources are then turned off at the
completion of the test.
The voltage and current waveforms for the two versions
of Figure 1 are shown in Figure 2.
4 Test Procedure
The procedures below describe how to set up the test
conditions and determine the acceptance limits for
implementing the transient thermal test for die
attachment evaluation using the apparatus and
definitions stated above.
4.1 Initial Device Testing Procedu re — The following
steps describe in detail how to set up the apparatus
described previously for proper testing of various
integrated circuit devices.
Step 1 — From a 10 to 15 piece sample of the
integrated circuits to be tested, pick any one device to
start the set-up process. Set up the test apparatus as
follows:
V
H
= 5.0 V (Or some other desired value near the
device under tests (DUT’s) normal operating
voltage.)
t
H
= 200 ms
t
MD
= 15 us
I
M
= 1.0 mA (Or some other value appropriate for
the specific device under test; typically in the range
of 80 uA to 9.9 mA.)
Step 2 — Insert device into the apparatus test fixture
and initiate a test.
(For best results, a test fixture that offers some form of
heat sinking would be desirable.)
Step 3 — If ∆V
F
is in the 20 to 40 mV range, then
proceed to the next step. This range corresponds to a
junction temperature change of roughly 10°C to 20°C
and is sufficient for initial comparison purposes.
If ∆V
F
is less than 20 mV, return to Step 1 and increase
heating power into device by increasing V
H
, or by
reconfiguring the DUT connections for greater power
dissipation, or a combination of both.
If ∆V
F
is greater than 80 mV, corresponding to a junc-
tion temperature change greater than 40°C, it would
probably be desirable to reduce the heating power by
returning to Step 1 and reducing V
H
, or by
reconfiguring the DUT connections to reduce power
dissipation, or a combination of the two. Reducing V
H
is the preferable approach.
Because two different devices can show the same rise
in junction temperature, even if the value of P
H
is
different, a comparison of the devices is best
accomplished using the CU value. As defined in
Section 2 above, CU provides a comparison unit that
takes into account different device I
H
values for a given
V
H
test condition.
SEMI G46-88 © SEMI 19883
Step 4 — Test each of the sample devices and record
the ∆V
F
and CU data as shown in Figure 3.
Step 5 — Select out the devices with the highest and
lowest values of CU and put the remaining devices
aside.
The ∆V
F
values can be used instead of CU if the mea-
sured values of I
H
are very tightly grouped aroung the
average value.
Step 6 — Following the Heating Time (t
H
) sequence
shown in Figure 4, read and record the ∆V
F
and CU
data values for each of the two devices of Step 5.
Step 7 — Using the data from the previous step,
prepare heating curves for the two devices in a manner
similar to the examples shown in Figure 5.
Step 8 — Interpretation of the heating curves is the next
step. Realizing that the thermal characteristics of
identical chips should be the same if the heating time
(t
H
) is less than or equal to the thermal time constant of
the chip, the two curves should start out the same for
the low values of t
H
. Non-identical chips (i.e., thinner or
smaller in cross section) will have completely different
curves, even at the smaller values of t
H
. As the value of
t
H
is increased, thereby overcoming the chip thermal
constant, heat will have propagated through the chip
into the die attachment region. Since the heating curve
devices of Step 5 were specifically chosen for their
difference, the curves of Figure 5 diverge after t
H
reaches a value where the die attachment variance has
an effect on the device junction temperature. Increasing
t
H
further will probably result in a flattening of the
curve as the heating propagates in the device package.
If the device package has little thermal mass and/or is
not well mounted to a good heat sink, the curve will not
flatten very much, but will show a definite change in
slope. Figure 6 shows the key elements of the heating
curve.
Step 9 — Using the heating curve, select the
appropriate value of t
H
to correspond to the inflection
point in the transition region between heat in the chip
and heat in the package.
If there are several different elements in the heat flow
path-chip, die attachment, substrate, substrate
attachment, and package, for example, in a hybrid there
will be several plateaus and transitions in the heating
curve. Appropriate selection of t
H
will optimize
evaluation sensitivity to other attachment areas.
Step 10 — Return to the apparatus and set t
H
equal to
the value determined from Step 9.
Step 11 — Because the selected value of t
H
is much less
than that for thermal equilibrium, it is possible to
significantly increase the heating power without
degrading or destroying the device. The increased
power dissipation within the device under test will
result in high ∆V
F
and/or CU values that will make
determination of acceptable and non-acceptable devices
much easier.
Step 12 — The pass/fail limit, the cutoff point between
acceptable and non-acceptable devices, can be
established in a variety of ways:
a) Correlation to other die attachment evaluation
methods, such as die shear and/or x-ray; while these
two methods have little actual value from a thermal
point of view, they do represent standardized methods
as described in MIL-STD specifications.
b) Maximum allowable junction temperature variation
between devices; since the relationship between ∆T
J
and ∆V
F
is about 0.5°C/mV, the junction temperature
spread between devicescan be easily determined. The
T
J
predicts reliability. Conversely, the T
J
spread neces-
sary to meet the reliability projections can be translated
to a ∆V
F
and/or CU value for a Pass/Fail criteria, based
on correlation with steady-state thermal equilibrium
conditions.
To fully use this approach, it will be necessary to
calibrate the devices for the exact value of the T
J
- V
F
characteristic. The characteristic’s slope, commonly
referred to as K Factor, is easily measured on a sample
basis using a voltmeter, environmental chamber,
temperature indicator and a power supply setup for
forcing, both active devices and thermal test chips as
shown in Figure 7. A simple set of equations yields the
junction temperature once K and ∆V
F
are known:
∆T
j
= | (K) (∆V
F
) |
T
J
= T
A
+ ∆T
j
Where T
A
is the ambient or reference temperature.
c) Statistically from a moderate size device sample; the
distribution of ∆V
F
or CU values should be a normal
one with defective devices out of the normal range.
Figure 8 shows a ∆V
F
distribution for a sample lot of
integrated ciruits. Note that the left-hand side of the
histogram envelope is fairly well-defined, but the other
side is greatly skewed to the right. This comes about
because the left-hand side is constrained by the
absolutely best heat flow that can be obtained with a
given chip assembly material and process. The other
side has no such constraints because there is no limit as
to how poorly a chip is mounted.
SEMI G46-88 © SEMI 1988 4
The usual rule of thumb in setting the maximum limit
for ∆V
F
or CU is to use the distribution average value
and one standard deviation ( σ) i.e. —
(∆V
F
)
high
limit
=∆V
F
+ X
σ
∆
(CU)
high
limit
= CU + X
σ
CU
Where X = 1 in most cases.
The statistical data required is obtained by testing 40 or
more devices under the conditions of Step 11.
Step 13 — Once the test conditions and pass/fail limit
have been determined, it is necessary only to record this
information for future testing requirements of the same
device in the same package. With the apparatus
properly set-up, including the fail limit selector on
those apparatus set ups so equipped, the operator need
only insert the device, initiate a test, and then either
read the ∆V
F
or CU display or observe the appropriate
pass or fail indicaors.
The steps listed hereto have been conveniently
summarized in Figure 9. The total time required to
perform these steps is greatly dependent on the operator
but, in general, should require about one hour if the
statistical approach of Step 12.C is used.
4.2
Routine Device Testing Proced ure — Once the
proper control settings have been determined for a
particular device type from a given manufacturing
process or vendor, repeated testing of that device type
simply requires that the same test conditions be used as
previously determined.
New device types or the same devices manufactured
with a different process will require a repeat of Section
4.1.
4.3
Comparison of Different Vend or Devices — Each
device type is defined as a specific chip manufactured
to a given set of procedures. Integrated circuit users
who buy a specific part number from more than one
vendor or manufacturers that redesign or otherwise
modify the fabrication of their devices will be able to
use the heating power and approximately the same t
H
for all vendors, but probably will have to use a different
∆V
F
or CU pass/fail limit for each different vendor
because the K Factor for parts manufactured by
different vendors will probably be different. The
difference can be determined in Step 12.B and using the
setup described in Figure 7.
5 Test Condition Specification
To properly set up the test apparatus and to insure
repeatable measurements, the following test conditions
must be fully specified:
a. V
H
b. t
H
c. I
M
d. t
MD
(and t
SW
if appropriate)
e. DUT/apparatus interface (i.e., wiring connection)
f. ∆V
H
or CU data requirement
Figure 1A
Set-Up for Junction Isolation Diode Devices
Figure 1B
Set-Up for Parisitic Diode or Thermal Test Chip
Temperature Sensing