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SEMI M10-1296 © SE MI 1987, 1996 3 scratch — (macroscratch , microscratch ): Long, n arro w, shallow groove or cut below the established p lane of the surface, s een either before or after etching. The ratio of the lengt…

SEMI M10-1296 © SEMI 1987, 1996 2

thickness of the slice. Often cracks are caused by the

improper handling of wafers.

NOTE Some crack-defect structures can be traced to process

related events.

cavity — (void) A vacancy or hole in the wafer.

NOTE Usually left by dissolved precipitates and Ga

inclusions, As disassociation or created by excess vapor

pressure.

Dimple — Deformation appearing in mechanically

polished GaAs wafers.

NOTE This surface texture can be induced by floating the

wafers during the initial stages of polishing.

Dislocation — See slip, lineage, pit.

edge chip — See chip.

Embedded — abrasive grains Abrasive particles

mechanically forced into the surface of the wafer.

etch pi t — See pit.

film — See contaminant.

flake — Material missing from one, but not the other,

side of a wafer, whose sole interior boundary is one

distinct line or arc not exceeding 2 mm in length, nor

projecting into the wafer beyond the specified edge

exclusion.

gallium inclusion — A segregated Ga-rich droplet

incorporated into the surface structure.

NOTE Normally caused by insufficient As vapor pressure at

the termination of the crystal growth process or by Ga

complexing with some dopants near saturation.

grain boundary — See lineage.

haze — (cloud, nebula): Attributable to light scattering

by concentrations of microscopic surface irregularities

such as pits, oxides, small ridges or scratches, particles,

etc. The light reflection from an individual irregularity

probably could not be readily detected by the unaided

eye, so haze is a mass effect. It is seen as a high density

of tiny reflections.

NOTE This type of contamination may occur during slicing,

lapping, or polishing.

lamella — A special case of the twin. A multiple twin,

extremely thin and relatively long, which may intersect

more than one plane.

lineage — (dislocation pits, grain boundary): Low-

angle grain boundary resulting from an array of

dislocations. This angle may vary from a fraction of a

second to a minute of arc difference in orientation from

one part of the crystal to another. The array of

dislocations will appear as rows of pits on a

preferentially etched surface.

NOTE Lineage can be induced into the material in crystal

growth or in subsequent thermal or epitaxial processes.

Lineage will be visible to the unaided eye only after

preferential etching.

macroscratch —See scratch.

microscratch — See scratch.

microtwin — See twin.

orange peel — (roughness, texture): Large featured

roughened type of surface visible to the unaided eye,

occasionally seen on all types of polished wafers.

NOTE Orange peel is usually symptomatic of a process

control problem. In the case of chemical polishing for

instance, an excessively fast polishing rate, or nonuniform

flow of oxidizer during polishing, can result in orange peel.

Conversely, it can also be caused by insufficient stock

removal.

particulate — (dust): Discrete particle of material

which can usually be removed by (non-etching)

cleaning.

pit — (dislocation, etch pit): Depression in the wafer

surface which has a definite and distinguishable shape,

that is, a place where the sloped sides of the pit meet

the wafer surface.

NOTE Pits can be caused by the various growths or polishing

processes.

Preferential etch pits result where dislocations intersect

the wafer surface after treatment with a preferential

etch. These pits so formed usually have a characteristic

shape related to the surface and bulk crystallographic

orientation.

polycrystalline — (poly): Body of semiconductor

materials that contain large-angle grain boundaries,

twin boundaries, or both.

precipitates — A localized concentration of dopant at

its solubility limit formed during crystal growth.

probe damage — Any damage to the wafer surface

caused by mechanical probing or measurement.

roughness — see orange peel.

saw blade defects —A depression in the wafer surface

made by the blade, which may not be visible before

polishing.

saw exit chip —A particular kind of edge chip, found at

the point where the saw blade completed its cut of the

wafer. It is typically flat or arc shaped instead of

irregular in shape, and can sometimes be confused with

the orientation flats.

SEMI M10-1296 © SEMI 1987, 19963

scratch — (macroscratch, microscratch): Long, narrow,

shallow groove or cut below the established plane of

the surface, seen either before or after etching. The ratio

of the length of the figure to the width of the figure

must be greater than 5:1 in order to be defined as a

scratch.

Macroscratches are visible to the unaided eye under

high intensity illumination.

Microscratches are not visible to the unaided eye

under high intensity illumination.

slip — (dislocation pit, preferential etch pits, stress

effect) (see also pit): Process of plastic deformation in

which one part of a crystal undergoes a shear

displacement relative to another in a fashion which

preserves the crystallinity of the material. Slip is

evidenced by a pattern of one or more straight lines of

10 or more dislocation etch pits per millimeter which

do not necessarily touch each other.

striations — Striations appear in Czochralski grown

crystals regardless of their resistivity.

tweezer mark — Any mark on the wafer caused by

handling with tweezers.

twin — A body of crystal within the wafer in which the

lattice is of two parts, related to each other in

orientation as mirror images, across a coherent planar

interface known as the twinning plane or twin

boundary.

NOTICE: These standards do not purport to address

safety issues, if any, associated with their use. It is the

responsibility of the user of these standards to establish

appropriate safety and health practices and determine

the applicability of regulatory limitations prior to use.

SEMI makes no warranties or representations as to the

suitability of the standards set forth herein for any

particular application. The determination of the

suitability of the standard is solely the responsibility of

the user. Users are cautioned to refer to manufacturer’s

instructions, product labels, product data sheets, and

other relevant literature respecting any materials

mentioned herein. These standards are subject to

change without notice.

The user’s attention is called to the possibility that

compliance with this standard may require use of

copyrighted material or of an invention covered by

patent rights. By publication of this standard, SEMI

takes no position respecting the validity of any patent

rights or copyrights asserted in connection with any

item mentioned in this standard. Users of this standard

are expressly advised that determination of any such

patent rights or copyrights, and the risk of infringement

of such rights, are entirely their own responsibility.

International), 3081 Zanker Road, San Jose, CA 95134. Reproduction o

the contents in whole or in part is forbidden without express written

consent of SEMI.

SEMI M11-0704 © SEMI 1988, 2004 1

SEMI M11-0704

SPECIFICATIONS FOR SILICON EPITAXIAL WAFERS FOR

INTEGRATED CIRCUIT (IC) APPLICATIONS

This specification was technically approved by the Global Silicon Wafer Committee and is the direct

responsibility of the North American Silicon Wafer Committee. Current edition approved by the North

American Regional Standards Committee on April 22, 2004. Initially available at www.semi.org June 2004;

to be published July 2004. Originally published in 1988; previously published November 2003.

1 Purpose

1.1 This specification defines and provides examples

of silicon epitaxial wafer requirements for integrated

circuit device manufacture. It is restricted to wafers of

diameter 100 mm or greater with epitaxial layer

thickness less than or equal to 25 µm. By defining

inspection procedures and acceptance criteria, both

suppliers and consumers may uniformly define product

characteristics and quality requirements.

2 Scope

2.1 This specification covers characteristics of both the

substrate (as specified in SEMI M1) and the epitaxial

layer, in-cluding handling and packaging. The primary

standard-ized properties set forth in this specification

relate to physical, electrical, and surface defect

parameters.

2.2 The primary standard-ized properties set forth in

this specification relate to physical, electrical, and

surface defect parameters.

2.3 A complete purchase specification requires that

additional physical properties be specified along with

suitable test methods for their measurements. SEMI

M18 may be used for this purpose.

2.4 These specifications are specifically directed to

silicon homoepitaxial deposits on homogeneous silicon

substrates only, for which more stringent uniformity

and surface defect criteria are required than specified in

SEMI M2.

NOTICE: This standard does not purport to address

safety issues, if any, associated with its use. It is the

responsibility of the users of this standard to establish

appropriate safety and health practices and determine

the applicability of regulatory limitations prior to use.

3 Referenced Standards

3.1 SEMI Standards

SEMI M1 — Specifications for Polished Mono-

crystalline Silicon Wafers

SEMI M2 — Specification for Silicon Epitaxial Wafers

for Discrete Device Applications

SEMI M18 — Format for Silicon Wafer Specification

Form for Order Entry

SEMI M43 — Guide for Reporting Wafer

Nanotopography

SEMI M44 — Guide for Conversion Factors for

Interstitial Oxygen in Silicon

SEMI M53 — Practice for Calibrating Scanning

Surface Inspection Systems using Certified Depositions

of Monodisperse Polystyrene Latex Spheres on

Unpatterned Semiconductor Wafer Surfaces

SEMI MF95 — Test Method for Thickness of Epitaxial

Layers of Silicon on Substrates of the Same Type by

Infrared Reflectance

SEMI MF110 — Test Method for Thickness of

Epitaxial or Diffused Layers in Silicon by the Angle

Lapping and Staining Technique

SEMI MF154 — Guide for Identification of Structures

and Contaminants Seen on Specular Silicon Surfaces

SEMI MF374 — Test Method for Sheet Resistance of

Silicon Epitaxial Layers Using an Inline Four-Point

Probe with the Single Configuration

SEMI MF398 — Test Method for Majority Carrier

Con-centration in Semiconductors by Measurement of

Wavelength of the Plasma Resonance Minimum

SEMI MF523 — Practice for Unaided Visual

Inspection of Polished Silicon Slices

SEMI MF525 — Measuring Resistivity of Silicon

Wafers Using a Spreading Resistance Probe

SEMI MF672 — Test Method for Measuring

Resistivity Profiles Perpendicular to the Surface of a

Silicon Wafer Using a Spreading Resistance Probe

SEMI MF723 — Practice for Conversion between

Resistivity and Dopant Density for Boron-Doped and

Phosphorus-Doped Silicon

SEMI MF951 — Test Method for Determination of

Radial Interstitial Oxygen Concentration Variation in

Silicon