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SEMI T14-1104 © SEMI 2004 7 RELATED INFORMATION 1 APPLICATION NOTES NOTICE : This related information is not an official part of SEMI ( doc# ) an d was derived fro m the Japanese Traceability committee. This related info…

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SEMI T14-1104 © SEMI 2004 6
Orientation Fiducial Axis
[011]
Notch
WAFER SURFACE
3.0 from
Orientation Fiducial Axis
Outer periphery of FQA
Edge Exclusive Area
Edge Profile region
Wafer Periphery
Orientation Fiducial Axis
[011] ± 1.0°
Notch
WAFER SURFACE
3.0 ± 0.1° from
Orientation Fiducial Axis
Outer periphery of FQA
Edge Exclusive Area
Edge Profile region
Wafer Periphery
R
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ID Mark Area
NOTE: Figure 5 is not to scale.
Figure 5
Data Matrix Code Location on Front Bevel Surface of Notched 300 mm Diameter Wafer
Top View
SEMI T14-1104 © SEMI 2004 7
RELATED INFORMATION 1
APPLICATION NOTES
NOTICE: This related information is not an official part of SEMI (doc#) and was derived from the Japanese
Traceability committee. This related information was approved for publication by full letter ballot on July 23, 2004.
R1-1 Shape and Size of the Protrusion Dot Mark
R1-1.1 A microdot mark is formed by laser irradiation and consists of a single dot mark on each laser-irradiated
point. The mark has a single protrusion, which includes a concave portion provided around the protrusion and lower
than a surface of the wafer and whose center potion protrudes upward so as to be higher than the surface of the
wafer. The length of each dot mark along the surface of the article to be marked should be 6.0 µm + 10% – 20%.
The protrusion height is more than 300 nanometers, formed on each laser irradiate point. (As shown in below Figure
R1-1.)
+10%
- 20%
A
A
A-A
H 300 nm
>
=
6.0 µm
H
NOTE: Figure R1-1 is not to scale.
Figure R1-1
Dot Height & Vertical Cross Section
R1-2 Location of Data Matrix Code Symbol
R1-2.1 Data matrix code location is defined on the front bevel of a 300 mm diameter notched wafer, whose side
view is referred from SEMI M1.
Back Grinded area
Polished Area by
Chemical Mechanical Polishing (CMP)
Remaining area for Micro ID
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NOTE: Figure R1-2 is not to scale.
Figure R1-2
Data Matrix Code Location on Front Bevel Surface of 300 mm Diameter Wafer
Side View
SEMI T14-1104 © SEMI 2004 8
RELATED INFORMATION 2
APPLICATION NOTES
NOTICE: This related information is not an official part of SEMI (doc#) and was derived from the Japanese
Traceability Committee. This related information was approved for publication by full letter ballot on July 23,
2004.
R2-1 References
R2-1.1 The following papers may be referred to understand Micro ID technology presented in this document.
1) Improvement in Reading Precision of Micro-ID Engraved on Wafer, ISSM2003, 2003/09/30
2) Micro-ID Technology for Single Wafer Management, ISSM2002, 2002/10/17
3) New Identification System for Individual Wafer Management, ISSM2000; Session II-6 (2000) Page 33,
2000/9/26
R2-2 SEMI Activities
R2-2.1 Additional information is gathered at 2
nd
round robin of the Micro ID Task Force. Many of such
information turned out to be excellent and valuable in reading the Micro ID.
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