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SEMI M1-0305 © SEMI 1978, 2005 8 50441/1 — Determi nation of the Ge ometric Dimensions of Semicond uctor Slices: Measurement of Thickne ss 50441/2 — Determination of t he Geomet ric Dime nsions of Sem iconductor Slices: …

SEMI M1-0305 © SEMI 1978, 2005 7

3.3 JEITA (formerly JEIDA) Standards

EM-3401 (43) — TERMINOLOGY OF SILICON WAFER FLATNESS

EM-3501 (18)— Standard Methods for Determining the Orientation of a Semiconductive Silicon Single Crystal

EM-3502 (53) — Test method for recombination lifetime in silicon wafers by measurement of photoconductivity

decay by microwave reflectance

EM-3503 (56)— Standard test method for substitutional atomic carbon content of silicon by infrared absorption

EM-3504 (61) — Standard test method for interstitial atomic oxygen content of silicon by infrared absorption

EM-3601 — Standard Specification for Dimensional Properties of Silicon Wafers with Specular Surfaces

EM-3602 (27) — Standard specification for dimensional properties of silicon wafers with specular surfaces

EM-3603 — Standard of SOI wafers and metrology

3.4 JIS Standards

H 0604 — Measuring of minority-carrier life time in silicon single crystal by photoconductive decay method

H 0607 — Determination of Conductivity Type in Germanium by Thermoelectromotive Method

H 0609 — Test methods of crystalline defects in silicon by preferential etch techniques

H 0611 — Methods of measurement of thickness, thickness variation and bow of silicon wafer

H 0614 — Visual inspection for silicon wafers with specular surfaces

H 0615 — Test method for determination of impurity concentrations in silicon crystal by photoluminescence

spectroscopy

Z 8741 — Specular glossiness — Methods of measurement

3.5 DIN Standards

50431 — Measurement of the Electrical Resistivity of Silicon or Germanium Single Crystals by Means of the Four-

Point-Probe Direct Current Method with Collinear Four-Probe Array

50432 — Determination of the Conductivity Type of Silicon or Germanium by Means of Rectification Test or Hot-

Probe

50433/1 — Determination of the Orientation of Single Crystals by Means of X-Ray Diffraction

50433/2 — Determination of the Orientation of Single Crystals by Means of Optical Reflection Figure

50433/3 — Determination of the Orientation of Single Crystals by Means of Laue Back Scattering

50434 — Determination of Crystal Defects in Monocrystalline Silicon Using Etching Techniques on {111} and

{100} Surfaces

50435 — Determination of the Radial Resistivity Variation of Silicon or Germanium Slices by Means of a Four-

Point-DC-Probe

50438/1 — Determination of Impurity Content in Silicon by Infrared Absorption: Oxygen

50438/2 — Determination of Impurity Content in Silicon by Infrared Absorption: Carbon

50440/1 — Measurement of Recombination Carrier Lifetime in Silicon Single Crystals by Means of

Photoconductive Decay Method; Measurement on Bar-Shaped Test Samples

2 Japan Electronics and Information Technology Industries Association, 3

floor, Mitsui Sumitomo Kaijo Bldg. Annex, 11, Kanda-Surugadai 3-

chome, Chiyoda-ku, Tokyo 101-0062, Japan. Telephone: 81.3.3518.6434; Fax: 81.3.3295.8727; Website:

www.jeita.or.jp

3 Japanese Industrial Standards, Available through the Japanese Standards Association, 1-24, Akasaka 4-Chome, Minato-ku, Tokyo 107-8440,

Japan. Telephone: 81.3.3583.8005; Fax: 81.3.3586.2014 Website:

www.jsa.or.jp

4 Deutches Institut für Normung e.V., standards are available in both English and German editions from Beuth Verlag GmbH, Burggrafenstrasse

6, 10787 Berlin, Germany, Telephone: 49.30.2601-0, Fax: 49.30.2601.1263, Website:

www.beuth.de

SEMI M1-0305 © SEMI 1978, 2005 8

50441/1 — Determination of the Geometric Dimensions of Semiconductor Slices: Measurement of Thickness

50441/2 — Determination of the Geometric Dimensions of Semiconductor Slices: Testing of Edge Rounding

50441/3 — Measurement of the Geometric Dimensions of Semiconductor Slices; Determination of Flatness

Deviation of Polished Slices by Means of Multiple Beam Interference

50441/4 — Determination of the Geometrical Dimensions of Semiconductor Slices: Diameter and Flat Depth of

Slices

50443/1 — Recognition of Defects and Inhomogenities in Semiconductor Single Crystals by X-Ray Topography:

Silicon

50445 — Contactless Determination of the Electrical Resistivity of Semiconductor Wafers with the Eddy Current

Method

3.6 ANSI Standards

ANSI/ASQC Z1.4 — Sampling Procedures and Tables for Inspection by Attributes

ANSI/EIA 556-B — Outer Shipping Container Standard

3.7 ISO Standard

ISO 14706 — Surface chemical analysis — Determination of surface elemental contamination on silicon wafers by

total reflection X-ray fluorescence spectroscopy (TXRF)

NOTICE: Unless otherwise indicated, all documents cited shall be the latest published versions.

4 Terminology

4.1 Terms and acronyms associated with silicon wafers and silicon technology are listed and defined in SEMI M59.

5 Ordering Information

5.1 Purchase orders for silicon wafers furnished to this specification shall include the following items. These items

are indicated on the Silicon Wafer Specification Format for Order Entry, Parts 1 and 2, shown in Table 1 with a 

symbol in the left-most column.

5.1.1 Growth Method.

5.1.2 Crystal Orientation.

5.1.3 Conductivity type.

5.1.4 Dopant.

5.1.5 Wafer surface orientation.

5.1.6 Resistivity.

5.1.7 Diameter.

5.1.8 Fiducial dimensions and orientation.

5.1.9 Edge profile.

5.1.10 Thickness and tolerance.

5.2 In addition, the purchase order must indicate the test method to be used in evaluating each of those items for

which alternate test procedures exist.

5.3 The following items must also be included in the purchase order:

5 American National Standards Institute, New York Office: 25 West 43rd Street, New York, NY 10036, USA. Telephone: 212.642.4900, Fax:

212.398.0023, Website:

www.ansi.org

6 International Organization for Standardization, ISO Central Secretariat, 1, rue de Varembé, Case postale 56, CH-1211 Geneva 20, Switzerland.

Telephone: 41.22.749.01.11; Fax: 41.22.733.34.30 Website:

www.iso.ch

5.3.1 Lot acceptance procedures.

5.3.2 Certification (if required).

5.3.3 Packing and shipping container labeling requirements.

5.4 Finally, many other characteristics may be specified in purchase orders for silicon wafers.

5.4.1 These shall be selected from the other items listed in the Silicon Wafer Specification Format for Order Entry,

Parts 1 and 2 (see Table 1).

5.4.1.1 The parameter values provided in the requirements tables in §6 may be used to identify appropriate values in

the specification without selecting a value for each line. However, even if these requirements table values are used,

the desired test methodology must be selected in accordance with ¶5.2.

5.4.2 It is essential that all choices for the items selected to be specified be made in order not to have unspecified

parameters that would lead to surprises between supplier and customer. This is particularly important in the

specification of wafer site flatness, for which a variety of parameters must be selected as outlined in Appendix 1.

5.4.3 Of the various items listed, the following (listed in the order in which they appear in Table 1) are most often

selected, especially for wafers to be used for advanced integrated circuit manufacture:

 nominal edge exclusion (to define the fixed quality area),

 structural characteristics,

 wafer ID marking,

 total thickness variation (TTV or GBIR),

 warp (and sometimes bow or sori),

 site flatness (SFQR), and

 localized light scatterers (LLS).

6 Requirements

6.1 General Characteristics

6.1.1 The crystal growth method shall be modified Czochralski (Cz), float zone (FZ), or magnetic Czochralski

(MCz) as specified on the purchase order. In some cases, the supplier is given the option of selecting Cz or MCz.

6.1.1.1 If the Cz or MCz method is used for crystal growth, it may be permissible to utilize refined (previously

melted) polysilicon in the growth charge; when this is the case, the appropriate box should be checked..

6.1.2 The crystal orientation shall be as specified on the purchase order. Usually either (100) or (111) is specified,

but (110) is sometimes specified for polished wafers to be used for making SOI wafers. Occasionally, another

orientation, such as (311) or (511), is specified.

6.1.3 The conductivity type shall be either n or p.

6.1.4 The dopant shall be specified to match the conductivity type. In general, boron (B) is used for p-type

material, while phosphorus (P) is most commonly used for n-type material. For some applications, antimony (Sb) or

arsenic (As) are used to obtain

n-type wafers. For high power applications, neutron transmutation doping is often

used to obtain high resistivity n-type wafers.

6.1.5 The nominal edge exclusion, EE, specifies the diameter of the fixed quality area (FQA), which is given by the

nominal diameter minus 2·EE (see Figure 1). This quantity provides a center-referenced property.