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SEMI E124-1103 © SEMI 2003 13 RELATED INFORMATION 2 EXAMPLE APPLICATION NOTICE: Th is related information is not an official part of SEMI E124 a nd was derived from an exam ple developed by the task force using this guid…
SEMI E124-1103 © SEMI 2003 12
R1-1.8 Thus, if we set normalized production
efficiency to have a value of ½ at this average cycle
time, we get
()
()
()()
{}
()()
()
1
2
min ,
1
normalizing
exponent
normalizing
exponent
normalized
production
efficiency
production
efficiency
average critical
WIP WIP
average critical
WIP WIP
=
=
=
+−
(5)
and, taking logarithms of both sides,
2
1
log
2
()()
{}
()()
()
()()
{}
()()
2
2
min ,
log
1
min ,
log
1
normalizing
exponent
average critical
WIP WIP
average critical
WIP WIP
average critical
WIP WIP
normalizing
exponent
average critical
WIP WIP
=
+−
=×
+−
(6)
so
()
()()
{}
()()
()()
()()
{}
()()
2
2
2
2
1
log
2
min ,
log
1
1
1
log
min ,
1
log
normalizing
exponent
average critical
WIP WIP
average critical
WIP WIP
average critical
WIP WIP
average critical
WIP WIP
average critical
WIP WIP
=
+−
−
=
+−
−
=
+
()()
{}
1
min ,
average critical
WIP WIP
−
(1)
which is the same as Equation (9) that was given in
Section 6 of the main body of this guide.
SEMI E124-1103 © SEMI 2003 13
RELATED INFORMATION 2
EXAMPLE APPLICATION
NOTICE: This related information is not an official part of SEMI E124 and was derived from an example
developed by the task force using this guide. This related information was approved for publication by full letter
ballot on April 11, 2003.
R2-1
R2-1.1 As an example to show how the metrics in this
guide are applied, the diagram in Figure R2-1 shows the
process flow for a grossly simplified model of a wafer
fab (developed by Karl Kempf at Intel) that has only
five machines in three tool sets, one process flow with
six steps, and a single material handling vehicle (that
transports 25 wafers at a time).
Diffusion
Dry Etch
Lithography
Figure R2-1
MiniFab Process Flow
R2-1.2 The data for this model are shown in the first
few columns of Table R2-1 and Table R2-2. A
simulation gave the following additional run data:
total time = 9 years = 4,733,640 minutes
average cycle time = 1.8 days = 2,592 minutes
total units out = 39,420 lots = 985,500 wafers
finished units out = 938,571 wafers
scrapped units out = 46,929 wafers
good unit equivalents out = 891,642.1 wafers
R2-1.3 In the next-to-last column of Table R2-1, we
added together (for each step) all of the times (to load,
process batch, unload, and travel to next step) and
summed the results to get a theoretical cycle time of
812.4 minutes. In the last column of Table R2-1, we
computed the theoretical production time per unit for
each step. These values were then used in the last
column of Table R2-2 to compute the throughput rate
for each equipment set. The throughput rate for the
lithography equipment set (0.2182 wafers/minute) is the
bottleneck throughput rate, not because it is the
smallest throughput rate (it is), but because the
lithography equipment set has the highest average
operational efficiency. The remaining terms are
derived on the following pages.
Table R2-1 Process Data
Process
Step
Number
Equipment
Set
Name
Time to
Load
Batch,
minutes
Time to
Process
Batch,
minutes
Time to
Unload
Batch,
minutes
Time to
Travel to
Next Step,
minutes
theoretical
cycle time
(See Note 1),
minutes
theoretical production
time per unit
(See Note 2),
minutes/wafer
1 Diffusion 20 225 40 8 293 3.0
2 Dry Etch 15 30 15 4 64 1.2
3 Lithography 10 2.2 10 4 26.2 2.2
4 Dry Etch 15 50 15 8 88 2.0
5 Diffusion 20 255 40 4 319 3.4
6 Lithography 10 2.2 10 - 22.2 2.2
Sum - 90 564.4 130 28 812.4 -
NOTE 1: (theoretical cycle time) = (Time to Load Batch) + (Time to Process Batch) + (Time to Unload Batch) + (Time to Travel to Next Step)
NOTE 2: (theoretical production time per unit) = (Time to Process Batch)/(Process Batch Size)
SEMI E124-1103 © SEMI 2003 14
Table R2-2 Equipment Data
Equipment
Set
Name
Number
in
Set
Process
Batch Size,
wafers
Buffer
Size,
wafers
Average
operational
efficiency
availability
efficiency
(each tool)
Average
availability
efficiency
bottleneck throughput
rate (See Note 1),
wafers/minute
Diffusion 2 75 450 88% 93% & 97% 95% 0.2969
Dry Etch 2 25 300 78% 81% & 85% 83% 0.5188
Lithography 1 1 300 91% 96% 96% (max!) 0.2182
Transport 1 25 0 69% 62% 62% 0.5536
NOTE 1: (bottleneck throughput rate) = (Number in Set) × (Average availability efficiency)/Σ(theoretical production time per unit)
() ()
[][]
[][]
[][]
[][]
450 75 2 300 25 2
300 1 1 0 25 1
450 150 300 50
300 1 0 25
600 350 301 25
1276 wafers
Process Size
WIP Buffer
Batch of
capacity Size
Size Set
eE
=+×
∈
=+×++×
+ + × + + ×
=+++
+ + + +
=+++
=
∑
(1)
(
)
938,571 wafers
4,733,640 minutes
wafers
0.1983
minute
f
inished units out
actual
throughput rate
total time
=
=
≈
(2)
(
)
(
)
(
)
()
wafers
2592 minutes 0.19827
minute
513.9 wafers
average average actual
WIP cycle time throughput rate
=×
≈×
≈
(3)
(
)
938,571 wafers
513.9 wafers
1826.3 turns
f
inished units out
WIP
turnover
average WIP
=
≈
≈
(4)
(
)
()
{}
min ,
1276 wafers wafers
min , 0.2182
812.4 minutes minute
wafers
min 1.5707, 0.2182
minute
0
WIP
theoretical
bottleneck
capacity
throughput throughput
theoretical
rate
rate
cycle time
=
≈
≈
≈
wafers
.2182
minute
(5)
(
)
()
{}
-
min ,
513.9 wafers wafers
min , 0.2182
812.4 minutes minute
wafers
min 0.6326, 0.2182
minute
0.2
average
best case bottleneck
WIP
throughput throughput
theoretical
rate rate
cycle time
=
≈
≈
≈
wafers
182
minute
(6)
()
()
-
max ,
513.9 wafers
max 812.4 minutes,
wafers
0.2182
minute
max 812.4 minutes, 2355.5 minute
average
best
WIP
case theoretical
cycle cycle time
bottleneck
time
throughput
rate
=
≈
≈
{}
s
2355.5 minutes≈
(7)
NOTE 1: For this average WIP level, the best-case cycle time
was not determined by the theoretical cycle time, but by the
bottleneck throughput rate. Thus, a simple metric like
(average cycle time)/(theoretical cycle time) underestimates
how well the factory is doing.