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SEMI G80-0200 © SE MI 2000 11 end test_cy cle end amplitude end pin measured instrumentation jitter = RMS spread of oscilloscope trigger (met hod descri bed furth er in Appen dix 4) actual RMS sig nal jitter = measured s…

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SEMI G80-0200 © SEMI 2000 10
10.4.5.1 This can be done by making period measure-
ments of the high speed clock channel under test, with a
high bandwidth, digital sampling oscilloscope. A 50-
ohm probe should be used to minimize measurement
jitter. The tolerance for this test is ± 20ps
(min-max)
due to the tester/instrument interaction using a generic
measurement method. The measurement results are
expressed as RMS. This measurement depends on the
jitter distribution being Gaussian. Reference Appendix
4 for additional detail regarding this measurement. If in
the application of this method it is determined that the
jitter is non-Gaussian, skip this test and make the
appropriate notation on the exceptions page (Appendix
3). The following nested loop outline describes the test
flow:
for pin = (all high speed clock pins)
for amplitude = 3V
for test_cycle = 10*min to min by min
for clock_delay = 50%
for i = 1 to 1000
meas(i) = measure the period of the clock pin under
test
end i
measured signal jitter = RMS spread of meas(1)
through meas(1000)
end format_delay
end test_cycle
end amplitude
end pin
measured instrumentation jitter = RMS spread of
oscilloscope trigger
(method described further in Appendix 4)
actual RMS signal jitter = measured signal jitter -
measured instrumentation jitter
(via sum of squares - reference Appendix 4)
Reference load B (50 ohms to ground) should be used
for this measurement.
Trigger
Edge
Measure
Jitter
10.4.4
& 10.4.5
Cycle Jitter
Trigger
Edge
Measure
Jitter
10.4.6
Phase (PW) Jitter
Figure 5
Jitter Tests – Sections 10.4.4, 10.4.5 and 10.4.6
10.4.6 High Speed Clock Self-trigger Phase Jitter Test
— If the ATE is configured with dedicated high speed
clock pins, an external instrument must be used to
measure short term, phase (or duty cycle) instability.
This can be done by making pulse width measurements
of the high speed clock channel under test, using a high
bandwidth, digital-sampling oscilloscope. A 50-ohm
probe should be used to minimize measurement jitter.
The tolerance for this test is ± 20ps
14
(min-max) due to
the tester/instrument interaction using a generic
measurement method. The results are expressed as
RMS.
10.4.6.1 This measurement depends on the jitter
distribution being Gaussian. Reference Appendix 4 for
additional detail regarding this measurement. If in the
application of this method it is determined that the jitter
is non-Gaussian, skip this test and make the appropriate
notation on the exceptions page (Appendix 3). The
following nested loop outline describes the test flow:
for pin = (all high speed clock pins)
for amplitude = 3V
for test_cycle = 10*min to min by min
for clock_delay = 50%
for i = 1 to 1000
meas(i) = measure the pulse width of the clock pin
under test
end i
measured signal jitter = RMS spread of meas(1)
through meas(1000)
end format_delay
14 When recording measurement data, log all measurements as they are taken
from the measurement equipment and show the associated equipment tolerance
as a separate entity.
SEMI G80-0200 © SEMI 200011
end test_cycle
end amplitude
end pin
measured instrumentation jitter = RMS spread of
oscilloscope trigger
(method described further in Appendix 4)
actual RMS signal jitter = measured signal jitter -
measured instrumentation jitter
(via sum of squares - reference Appendix 4)
Reference load B (50 ohms to ground) should be used
for this measurement.
11 Data Collection Tables
11.1 Table 1 is the data collection table. Data can be
manually or automatically entered to this table as this
procedure is executed, depending upon how the user
chooses to implement data collection.
11.2 Table 2 is intended to contain the final
conclusions or analysis results of this procedure. Data
for this table is taken from Table 1. Instructions for
entering data to Table 2 will be described in Section 12,
Reporting and Interpretation of Results, of this
procedure. Examples of OTA calculations and data
entry to Table 2 are contained in Appendix 2.
NOTE 4: A blank version of Table 2 is contained in Appendix
1.
12 Reporting and Interpretation of Results
12.1 Reporting Results — A large amount of data will
be gathered when this Test Method is executed per the
requirements of this method. A subset of this data
should be collected into Table 1. This table contains the
minimum and maximum values for the various tests
contained in this Test Method.
12.1.1 Table 2 is a summary revealing the results of
this Test Method. Table 2 entries will be determined
from values taken out of Table 1 as well as summations
of various entries occurring in Table 2. The following
is a guide to making entries to Table 2:
12.1.2 Driver Input Timing Delay Error (Section
10.4.1) — This value is taken from Table 1. It is the
difference between the minimum and maximum values
shown in Table 1 for this parameter.
12.1.3 Driver Input Timing Cycle Jitter (Section
10.4.4) — This value is taken from Table 1. This is the
RMS values shown in Table 1 for this parameter.
12.1.4 Driver Input Transition Time Variation
(Section 10.4.3) — This value is taken from Table 1. It
is the difference between the minimum and maximum
values shown in Table 1 for this parameter.
12.1.5 Driver Input Edge Placement Accuracy —
Driver Input Edge Placement by definition is the
summation of Driver Input Timing Delay Error
(Section 10.4.1), Driver Input Timing Cycle Jitter
(Section 10.4.4), and Driver Input Transition Time
Variation (Section 10.4.3). Regardless, since Drive
Input Timing Delay Error measurements defined in this
method do not exclude edge transition variation and
jitter this entry is simply the measurements results
obtained for Drive Input Timing Delay Error Level 2
(Section 10.4.1). Enter this value into Table 2 as Driver
Input Edge Placement.
12.1.6 Compare Output Time Delay Error (Section
10.4.2) — This value is taken from Table 1. It is the
difference between the minimum and maximum values
shown in Table 1 for this parameter.
12.1.7 Compare Output Edge Placement Accuracy —
Compare Output Edge Placement will be entered into
Table 2 as the same entry made for Compare Output
Time Delay Error (Section 10.4.2).
12.1.8 Drive Input to Compare Output Timing
Accuracy — Data taken from Table 1 for Section 10.3.1
results: Drive Input To Compare Output Timing
Accuracy = Reference – [(Min Value + Max Value)/2].
Refer to examples in Appendix 2.
12.1.9 Overall Timing Accuracy (OTA) — By
definition and in the general case, the OTA value is the
sum of Driver Input Edge Placement Accuracy,
Compare Output Edge Placement Accuracy, and Driver
Input to Compare Output Timing Accuracy. Examples
are provided in Appendix 2 for making this entry into
Table 2.
NOTE 5: For all High Speed Clock parameters shown in
Table 2: High Speed Clock Delay and High Speed Clock
Transition are parameters that use the same procedures as
Drive Input Timing Delay and Drive Input Transition Time
Variation. High Speed Clock Delay and High Speed Clock
Transition are parameters provided in this procedure to
accommodate those systems that have different pin
electronics for the High Speed Clock function. If the system
under evaluation doesn't have a High Speed Clock function,
then the steps in this procedure for all High Speed Clock
Accuracy are not required. High Speed Clock Cycle Jitter
and High Speed Clock Phase Jitter are reference parameters
with their respective test provided in this procedure to reveal
accuracy for the High Speed Clock function when that
function is present.
12.1.10 High Speed Clock Delay Error (Section
10.4.1) — This value is taken from Table 1. It is the
difference between the minimum and maximum values
shown in Table 1 for this parameter.
12.1.11 High Speed Clock Cycle Jitter (Section 10.4.5)
— This value is taken from Table 1. This is the RMS
values shown in Table 1 for this parameter.
SEMI G80-0200 © SEMI 2000 12
12.1.12 High Speed Clock Transition Time Variation
(Section 10.4.3) — This value is taken from Table 1. It
is the difference between the minimum and maximum
values shown in Table 1 for this parameter.
12.1.13 High Speed Clock Phase Jitter (Section
10.4.6) — This value is taken from Table 1. This is the
RMS values shown in Table 1 for this parameter.
12.1.14 High Speed Clock Accuracy — This
parameter is for systems that have a High Speed Clock
function. High Speed Clock Accuracy is simply the
same entry made for High Speed Clock Delay Error.
High Speed Clock Transition Time Variation, High
Speed Clock Cycle Jitter, and High Speed Clock Phase
Jitter are reference parameters and should be entered to
the appropriate location in Table 2.
12.1.15 Driver Input Z Timing Errors (Section 10.3.5)
— There are four Drive Input Z Timing Errors. Each
value is determined in the same way and is to be
entered into Table 2. This value is taken from Table 1.
Data to enter here is Positive Error and Negative Error
per the data in Table 1 and Equation 1, Appendix 2.
12.1.16 Timing Linearity (Section 10.3.1) — This
value is established from Table 1. Data to enter here is
Positive Error and Negative Error per the data in Table
1 and Equation 1, Appendix 2. These two values
should be entered at the appropriate place in Table 2.
12.1.17 Extended Delay (Section 10.3.4) — This value
is taken from Table 1. Data to enter here is Positive
Error and Negative Error per the data in Table 1 and
Equation 1, Appendix 2.
12.1.18 Multiple Period (Section 10.3.6) — This
parameter is optional. The test method for this
parameter was defined for those systems with Timing
On the Fly (OTF). If the system under evaluation does
not have OTF timing data entry for this parameter is not
required. Else, this value is taken from Table 1. Data
to enter here is Positive Error and Negative Error per
the data in Table 1 and Equation 1, Appendix 2.
12.2 Interpreting Results — Table 2 will contain
summarized data, results of the Overall Digital Timing
Accuracy Analysis Method for automated test systems.
12.2.1 This dialog is intended to explain the Level 1
and Level 2 results for OTA contained in Table 2 and
require reference to Figure 6, Figure 7
15
, and Table 2.
12.2.2 Level 1 analysis is meant to determine a test
system’s net conformance to the OTA specification in
an efficient manner.
15 Additional information related to Figure 7 is contained in
Appendix 2.
12.2.3 Level 2 employs external equipment to isolate
parameters that contribute to OTA. That data reveals a
more detailed and accurate representation to OTA
conformance. Regardless, there is a limitation at
getting to OTA entirely through Level 2 data collection.
12.2.4 Level 1 and Level 2 parameters are contained
in Table 2 to represent OTA (Overall Timing
Accuracy). Level 1 Timing Linearity (Section 10.3.1)
provides analysis for all pins under comprehensive
conditions and is used to acquire the drive input to
compare output error parameter. Extended Delay
(Section 10.3.4) complements Timing Linearity by
verifying accuracy for timing generator delays beyond
the length of the test cycle, and can be (optionally) used
in lieu of Section 10.3.1. These two Level 1 elements
represent in part OTA. Thus, this method produces a
single point representation of system OTA, per the
methodology defined in this method and consistent with
the definition of OTA. This is done by summing Level
2 Drive Input Edge Placement Accuracy and Compare
Output Edge Placement Accuracy with Level 1 Drive
Input to Compare Output Timing Accuracy.
12.2.4.1 Compare side error in this method is not fully
characterized or broken out into its constituent compo-
nents, per the defintion of Compare Output Edge Place-
ment Error. This method does establish Output Timing
Delay Error, and its measurement contains the jitter
component. But the method does not contain a way for
determining Output Compare Timing Jitter by itself.
12.2.5 Establishing OTA using only Level 2 data is
not possible. Only two of the three components per the
standard definition of OTA can be determined. The
OTA definition states: OTA is the sum of Drive Input
Edge Placement, Compare Output Edge Placement, and
Drive Input to Compare Output Accuracy. Level 2
analysis will collect data for the first two error
components. The Level 2 parameter not achievable is
Drive Input to Compare Output Accuracy. Level 1 will
determine that value.
12.2.5.1 The Drive Input to Compare Output Accuracy
by definition is the difference between the average of
min & max drive input delay timing and the average of
min & max compare output delay timing. Values for
those components are in the Level 2 data, but because
there is no common reference point for these two
components when the data is taken, their difference
cannot be established from the data at-hand.
12.2.5.2 In summary Level 2 analysis is capable of
independently determining and isolating drive input
timing error and compare output timing error. But,
Level 2 drive input to compare output-timing error can
not be established. Analysis done in Level 1 is required