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SEMI M61-0705 © SEMI 2005 5 6.5 Wafers s hall meet all requirements related to ot her charact eristics, if any such require ments are specified in the purchase order. 7 Sampling 7.1 Unless ot herwise specified, appropri …
SEMI M61-0705 © SEMI 2005 4
6.3.4 The pattern step height A as shown in Figure 3, shall meet the nominal value X within the tolerance Y, as
specified in nanometers (nm).
Figure 3
Cross-Sectional View of Epitaxial Substrate After Oxide Removal but Before Deposition of the Epitaxial Layer
Showing the Pattern Step Height, A
6.3.5 The defect density on the surface after deposition but before growth of the epitaxial layer shall not exceed the
density specified in number of defects per square centimeter.
6.4 Buried Layer Pattern Characteristics after Growth of the Epitaxial Layer
6.4.1 The pattern shift ratio d/t (see Figure 4) shall meet the specified requirements for nominal value X and
tolerance ±Y, both of which are dimensionless because both d and t are in micrometers (µm).
Figure 4
Cross-Section View of Epitaxial Wafer Showing the Pattern Shift, d.
Not to scale: AM = MB and CN = ND
6.4.2 The pattern distortion ratio shall not exceed the maximum value specified. This dimensionless ratio is equal
to
t
ba
ratio distortionpattern (1)
where:
a = width of pattern on epitaxial layer,
b = width of pattern on substrate, and
t = thickness of epitaxial layer
as shown in Figure 5
Figure 5
Cross-Section View of Epitaxial Layer Showing the Pattern Widths, a,
at the Epi Surface, and b, at the Layer-Substrate Interface
SEMI M61-0705 © SEMI 2005 5
6.5 Wafers shall meet all requirements related to other characteristics, if any such requirements are specified in the
purchase order.
7 Sampling
7.1 Unless otherwise specified, appropriate sample sizes shall be selected from each lot in accordance with
ANSI/ASQC Z1.4. Each quality characteristic shall be assigned an acceptable quality level (AQL) or lot tolerance
percent defective (LTPD) value in accordance with ANSI/ASQC Z1.4 definitions for critical, major, and minor
classifications. If desired and so specified in the contract or order, each of these classifications may alternatively be
assigned cumulative AQL or LTPD values. Inspection levels shall be agreed upon between the supplier and the
customer.
8 Test Methods
8.1 Because no test methods have been standardized and identified in Table 1, all tests to be made to assure that the
wafers meet the required characteristics shall be agreed upon between supplier and customer.
9 Certification
9.1 Upon request of the customer in the contract or order, a manufacturer’s or supplier’s certification that the
material was manufactured and tested in accordance with this specification, together with a report of the test results,
shall be furnished at the time of shipment.
9.2 In the interest of controlling inspection costs, the supplier and the customer may agree that the material shall be
certified as “capable of meeting” certain requirements. In this context, “capable of meeting” shall signify that the
supplier is not required to perform the appropriate tests. However, if the customer performs the test and the material
fails to meet the requirement, the material may be subject to rejection.
10 Product Labeling
10.1 The wafers supplied under these specifications shall be identified by appropriately labeling the outside of each
box or other container and each subdivision thereof in which it may reasonably be expected that the wafers will be
stored prior to further processing. Identification shall include as a minimum the nominal diameter, conductivity
type, dopant, orientation, resistivity range, and lot number. The lot number, either (1) assigned by the original
manufacturer of the wafers, or (2) assigned subsequent to wafer manufacture but providing reference to the original
lot number, shall provide easy access to information concerning the fabrication history of the particular wafers in
that lot. Such information shall be retained on file at the manufacturer’s facility for at least one month after that
particular lot has been accepted by the customer.
11 Packing
11.1 Special packing requirements shall be subject to agreement between the supplier and customer. Otherwise, all
wafers shall be handled, inspected, and packed in such a manner as to avoid chipping, scratches, and contamination
and in accordance with the best industry practices to provide ample protection against damage during shipment.
NOTICE: SEMI makes no warranties or representations as to the suitability of the standards set forth herein for any
particular application. The determination of the suitability of the standard is solely the responsibility of the user.
Users are cautioned to refer to manufacturer's instructions, product labels, product data sheets, and other relevant
literature, respecting any materials or equipment mentioned herein. These standards are subject to change without
notice.
By publication of this standard, Semiconductor Equipment and Materials International (SEMI) takes no position
respecting the validity of any patent rights or copyrights asserted in connection with any items mentioned in this
standard. Users of this standard are expressly advised that determination of any such patent rights or copyrights, and
the risk of infringement of such rights are entirely their own responsibility.
Copyright by SEMI® (Semiconductor Equipment and Materials
International), 3081 Zanker Road, San Jose, CA 95134. Reproduction of
the contents in whole or in part is forbidden without express written
consent of SEMI.
SEMI PR9-0705 © SEMI 2005 1
SEMI PR9-0705
PROPOSED GUIDE FOR STANDARD PERFORMANCE, PRACTICES,
AND ASSEMBLY FOR ULTRA HIGH PURITY MICROSCALE FLUIDIC
SYSTEMS FOR USE IN SCALABLE PROCESS ENVIRONMENTS
This proposed guide was technically approved by the global MEMS Committee. This edition was approved
for publication by the global Audits and Reviews Subcommittee on April 17, 2005. It was available at
www.semi.org in June 2005 and on CD-ROM in July 2005.
1 Purpose
1.1 This document provides guidelines for generic fluidic I/O design and fabrication that can reduce redundant
engineering effort and lead to improved design, manufacturability, testing and operation.
2 Scope
2.1 This includes guidance for performance, practices, and assembly of microscale fluidic components. This
document will provide guidance to users involved in design and development of standard fluidic interfaces.
NOTICE: This standard does not purport to address safety issues, if any, associated with its use. It is the
responsibility of the users of this standard to establish appropriate safety and health practices and determine the
applicability of regulatory or other limitations prior to use.
3 Limitations
3.1 This guide is a work in progress. Some sections require further development. Suggestions for improvement are
welcome.
4 Referenced Standards and Documents
4.1 SEMI Standards
SEMI F1 — Specification for Leak Integrity of High-Purity Gas Piping Systems and Components
NOTICE: Unless otherwise indicated, all documents cited shall be the latest published versions.
5 Terminology
(Refer to SEMI’s Compilation of Terms (COT) for a list of the most current terms and their definitions.)
5.1 Abbreviations and Acronyms
5.1.1 MEMS— Microelectromechanical systems
5.1.2 TLA — Three Letter Acronym
5.2 Definitions
5.2.1 Microscale — 10
6
meters.
5.2.2 Microfluidics — fluid transport, physics, and chemistry on microscale dimensions.
5.2.3 Micro Sealing Dimensions — flow channel cross sections having an effective diameter of <25 micrometers;
optionally flow channel cross sections having an effective diameter of 25 to 100 micrometers.
5.2.4 Macro Sealing Dimensions — flow channel cross sections having an effective diameter of >100 micrometers.
5.2.5 Microfluidic Components — fluidic components functioning at the scale of 1-100 micrometers. Examples:
micro flow channels, microvalves, micro pumps.
5.2.6 Microsealing Systems
5.2.7 Macro to Micro Sealing — sealing that connects the micro regime with the macro regime.
5.2.8 Microsealing — sealing on components at the microscale.