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SEMI M11-0704 © SEMI 1988, 2004 27 Table 8 Guide for the Specification of Polish ed Wafer, P+ Substrate for 0.25 µ m Design Rule Epitaxial CUSTOMER PART NUMBER : REVISION DATE: REQ. M18 ITEM # SPECIFICATION TESTING LEVEL…

SEMI M11-0704 © SEMI 1988, 2004 26

ITEM

p/p

EPITAXIAL

CIRCUIT WAFER

(DRAM)

p/p

EPITAXIAL

CIRCUIT WAFER

(Logic/DRAM)

p/p

EPIAXIAL

CIRCUIT WAFER

(Logic)

9.2-

9.5

OTHER none none none

9.6 Roughness NS (See Note 2.) NS (See Note 2.) NS (See Note 2.)

9.7

Brightness (Gloss) 60° angle of incidence,

referenced to a mirror polished wafer. NOTE:

Double-side polish process preferred

! 80% ! 80% Applies to

wafers without

backseal only.

! 80% Applies to

wafers without

backseal only.

9.X Localized Light Scatterers (See Note 6) NS (See Note 2.) NS (See Note 2.) NS (See Note 2.)

9.YA Scratches (Macro) none none none

9.YB Scratches (Micro) " 25 mm (total

length)

" 25 mm (total

length)

" 25 mm (total

length)

11.0 ADDITIONAL EPITAXIAL LAYER CHARACTERISTICS

11.1 Conductivity Type/Structure

p/p

11.2 Primary Dopant Boron Boron Boron

11.3 Silicon Source Gas NS (See Note 2.) NS (See Note 2.) NS (See Note 2.)

11.4 Epitaxial Growth Method NS (See Note 2.)

(see Item 5.3)

NS (See Note 2.)

(see Item 5.3)

NS (See Note 2.)

(see Item 5.3)

11.5 Net Carrier Density Target Variation (Center of

wafer)

user/supplier user/supplier user/supplier

11.6 Net Carrier Density Variation

± 5% ± 5% with backseal

± 10% without

backseal

± 5% with backseal

± 10% without

backseal

11.7 Thickness Target Variation

± 5% ± 5% ± 5%

11.8 Thickness Variation

± 10% ± 10% ± 10%

11.9 Transition Width user/supplier user/supplier user/supplier

11.X Layer Flat Zone user/supplier user/supplier user/supplier

13.1 Stacking Faults (See Note 7) < 2 per wafer < 2 per wafer < 2 per wafer

13.2 Slip/Dislocations (See Note 8) none none none

13.5-

13.13

OTHER (see Item 13.1) (see Item 13.1) (see Item 13.1)

NOTE 1: * indicates substrate specification.

NOTE 2: NS is the abbreviation for Not Specified.

NOTE 3: Practical non-destructive metrology did not exist at the time this document was approved.

NOTE 4: The site size is 32 mm × 25 mm. Partial sites are included. The metrology was being developed at the time this document was being

balloted.

NOTE 5: These values are mathematically consistent. The 0.09 µm count limit was transformed using draft international standard: ISO/DIS

14644-1 which follows the equation: 34 counts per wafer = 60 counts per wafer /(0.12 µm/ 0.09 µm)2.

NOTE 6: The process control capability is expected to be: " 500 @ ! 0.25 µm.

NOTE 7: The lot average density is < 0.0029/cm2.

NOTE 8: Tested per SEMI MF1726; a depth < 100 nm is acceptable.

SEMI M11-0704 © SEMI 1988, 2004 27

Table 8 Guide for the Specification of Polished Wafer, P+ Substrate for 0.25 µm Design Rule Epitaxial

CUSTOMER PART NUMBER: REVISION DATE:

REQ. M18 ITEM # SPECIFICATION TESTING LEVEL

WAFER TEST PIECE

100% SAMPLE 100% SAMPLE

POLISHED WAFER, EPITAXIAL SUBSTRATE - MUST MEET SEMI M1

15.1 Resistivity

0.005-0.010 Ω·cm or 0.010-0.020 Ω·cm

Substrate Resistivity Backseal Required

0.005–0.010 Ω·cm

yes

0.010–0.020 Ω·cm

user specified

15.2 Bulk Micro

Defects

user specified

Dopant Boron

15.4 Nominal Diameter 150 mm [ ]

200 mm [ ]

15.5 Primary Flat/

Notch

User specified per SEMI M1

15.6 Extrinsic Getter User specified

Intrinsic Getter User specified

15.7 Laser Mark

Identification

SEMI M13 [ ]

SEMI M12 [ ]

SEMI T1 [ ]

15.8 Oxygen

Concentration

maximum 30 ppma, Old ASTM

Inspection Sheet Certificate required in a standard format to be

determined.

SQC Data Sheet SQC required in a standard format to be

determined.

12. MECHANICAL CHARACTERISTICS: PRE EPITAXIAL

Total Thickness

Variation (TTV)

5 µm (GBIR)

12.5 Flatness/Site

" 0.25 µm (SFQR), site size 22 mm × 22 mm

including partial sites, PUA to be negotiated

13. FRONT SURFACE CHARACTERISTICS

13.2 Slip/Dislocations none

13.10 Edge Chips none per SEMI MF523, Section 12.3

13.14 Localized Light

Scatterers and

0.23 per cm

maximum ! 0.12 µm LSE and

0.0 per cm

! 1 µm LSE, calibrate using

SEMI M53

Scratches none

13.15 Nominal Edge

Exclusion

3 mm for all front surface characteristics

except cracks/fractures, edge chips, crow’s

feet, and foreign matter

Surface Metals " 1 × 10

atoms per cm

for each element:

Na, Al, Cr, K , Fe, Ni, Cu, Zn

14. BACK SURFACE CHARACTERISTICS

14.1 Contamination none per SEMI MF523, Section 12.4

SEMI M11-0704 © SEMI 1988, 2004 28

CUSTOMER PART NUMBER: REVISION DATE:

14.2 Back Seal [ ] Silicon Oxide: 5000 ± 1000 Angstroms,

[ ] Polysilicon: 10,000 ± 2000 Angstroms,

[ ] Backside Damage,

[ ] None,

[ ] Combination of: 3000 ± 1000 Angstroms

Silicon Oxide on top of 8000 ± 2000

Angstroms Polysilicon

Table 9 Guide For The Specification Of 0.13 Micron Design Rule Silicon Epitaxial Wafers

ITEM p/p

EPITAXIAL

CIRCUIT WAFER

(DRAM)

p/p

EPITAXIAL

CIRCUIT WAFER

(Logic/DRAM)

p/p

EPITAXIAL

CIRCUIT WAFER

(Logic)

1.0 GENERAL CHARACTERISTICS

1.1 Growth Method Cz or MCz * Cz or MCz * Cz or MCz *

1.2 Crystal Orientation {100} {100} {100}

1.3 Crystal Orientation/Tolerance ± 1° ± 1° ± 1°

1.4 Conductivity type p/p- p/p+ p/p++

1.5 Dopant Boron Boron Boron

1.6 Nominal Edge Exclusion 3 mm 3 mm 3 mm

2.0 ELECTRICAL CHARACTERISTICS

2.1.1 Resistivity (Center Point) 0.8–15 $·cm * 0.01–0.02 $·cm * 0.005–0.010 $·cm *

2.2 Radial Resistivity Variation

(See Note 9.)

< 20% * < 20% * < 20% *

2.3 Resistivity Striations NS * NS * NS *

3.0 CHEMICAL CHARACTERISTICS

3.1.1 Nominal Oxygen Concentration (Center) user/supplier user/supplier user/supplier

3.1.2 Oxygen Concentration Tolerance

Per old ASTM calibration factor (See

SEMI M44.)

± 2.0 ppma *

(See Note 3.)

± 2.0 ppma *

(See Note 3.)

3.2 Radial Oxygen Variation

Per SEMI MF951

" 10% *

10 mm from Edge

" 10% *

10 mm from Edge

(See Note 3.)

" 10% *

10 mm from Edge

(See Note 3.)

3.3 Carbon Concentration

(See Note 9.)

" 0.5 ppma * " 0.5 ppma

(See Note 3.) *

" 0.5 ppma

(See Note 3.) *

4.0 STRUCTURAL CHARACTERISTICS

4.1 Dislocation Etch Pit Density NS NS NS

4.2 Slip none none none

4.3 Lineage none none none

4.4 Twin none none none

4.5 Swirl none none none

4.6 Shallow pits none none none

4.7 Oxidation-Induced Stacking Faults (OSF) NS * NS * NS *

4.8 Oxide Precipitates (BMD) O

Reduction

(%O

)

user/supplier user/supplier user/supplier

5.0 WAFER PREPARATION CHARACTERISTICS

5.1 Wafer ID Marking per M1 per M1 per M1

5.2 Front Surface Thin Film(s) NS NS NS

5.3 Denuded Zone user/supplier user/supplier user/supplier