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SEMI M23-0703 © SEMI 1993, 2003 1 SEMI M23-0703 SPECIFICATION FOR POLISHED MONOCRYSTALLINE INDIUM PHOSPHIDE WAFERS This specification was technically approved b y th e Global Compound Sem i conductor Committee and is the…

SEMI M22-0303 © SEMI 1992, 2003 6

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SEMI M23-0703 © SEMI 1993, 2003 1

SEMI M23-0703

SPECIFICATION FOR POLISHED MONOCRYSTALLINE INDIUM

PHOSPHIDE WAFERS

This specification was technically approved by the Global Compound Semiconductor Committee and is the

direct responsibility of the North American Compound Semiconductor Committee. Current edition approved

by the North American Regional Standards Committee on November 27, 2001. Initially available at

www.semi.org December 2001; to be published March 2002. Originally published in 1993; previously

published October 2000.

NOTICE: The designation of SEMI M23 was updated

during the 0703 publishing cycle to reflect the addition

of SEMI M23.6.

1 Purpose

1.1 These specifications cover the substrate require-

ments for monocrystalline high-purity indium phos-

phide wafers used in semiconductor and electronic

device manufacturing. Dimensional and crystallo-

graphic orientation characteristics are the only standard-

ized properties set forth below.

1.2 A complete purchase specification may require that

additional physical, electrical, and bulk properties be

defined. These properties are listed together with test

methods suitable for determining their magnitude where

such procedures are documented.

2 Scope

2.1 These specifications are directed specifically to

indium phosphide wafers with one or both sides

polished. Unpolished wafers or wafers with epitaxial

films are not covered; however, purchasers of such

wafers may find these specifications helpful in defining

their requirements.

2.2 The material is Single Crystal Indium Phosphide

(InP) having a cubic zinc blende structure and the

following properties:

Density 4.787 g/cm

Melting Point

1062°C

Dielectric Constant 12.4

Lattice Parameter

5.869 Α at 27° C

Energy Gap 1.351 eV at 27° C

2.3 For reference purposes SI (System International,

commonly called metric) units shall be used.

2.4 This standard does not purport to address safety

issues, if any, associated with its use. It is the

responsibility of the users of this standard to establish

appropriate safety and health practices and determine

the applicability of regulatory limitations prior to use.

3 Referenced Standards

3.1 SEMI Standards

SEMI M39 — Test Method for Measuring Resistivity

and Hall Coefficient and Determining Hall Mobility on

Semi-Insulating GaAs Single Crystals

3.2 ASTM Standards

ASTM E122 — Practice for Choice of Sample Size to

Estimate Average Quality of a Lot or Process

ASTM F26 — Test Methods for Determining the

Orientation of a Semiconductive Single Crystal

ASTM F42 — Test Method for Conductivity Type of

Extrinsic Semiconducting Materials

ASTM F76 — Test Methods for Measuring Resistivity

and Hall Coefficient and Determining Hall Mobility in

Single Crystal Semiconductors

ASTM F84 — Test Methods for Measuring Resistivity

of Silicon Wafers with an In-Line Four-Point Probe

ASTM F154 — Practices and Nomenclature for

Identification of Structures and Contaminants Seen on

Specular Silicon Surfaces

ASTM F523 — Practice for Unaided Visual Inspection

of Polished Silicon Wafer Surfaces

ASTM F533 — Test Method for Thickness and

Thickness Variation of Silicon Wafers

ASTM F534 — Test Method for Bow of Silicon

Wafers

ASTM F613 — Test Method for Measuring Diameter

of Semiconductor Wafers

ASTM F657 — Test Method for Measuring Warp and

Total Thickness Variation on Silicon Wafers by Non-

Contact Scanning

ASTM F671 — Test Method for Measuring Flat Length

on Wafers of Silicon and Other Electronic Materials

1 American Society for Testing and Materials, 100 Barr Harbor

Drive, West Conshohocken, PA 19428-2959 (All cited standards

except for E122 may be found in Volume 10.05 of the Annual Book

of ASTM Standards; E122 may be found in Volume 14.02.)

SEMI M23-0703 © SEMI 1993, 2003 2

ASTM F673 — Test Method for Measuring Resistivity

of Semiconductor Slices or Sheet Resistance of

Semiconductor Films with a Noncontact Eddy-Current

Gage

ASTM F928 — Test Methods for Edge Contour of

Circular Semiconductor Wafers and Rigid Disk

Substrates

ASTM F1241 — Terminology of Silicon Technology

ASTM F1392 — Test Method for Determining Net

Carrier Density Profiles in Silicon Wafers by

Capacitance-Voltage Measurements with a Mercury

Probe

ASTM F1393 — Test Method for Determining Net

Carrier Density in Silicon Wafers by Miller Feedback

Profiler Measurements with a Mercury Probe

3.3 Other Standards

ANSI/ASQC

Z1.4-1993 — Sampling Procedures and

Tables for Inspection by Attributes

DIN

Standard Test Method 50454-2 — Determination

of the Dislocation Etch Pit Density in Monocrystals of

III-V Compound Semiconductors - Part 2: Indium

Phosphide.

DIN Test Method 50448 — Testing of Materials for

Semiconductor Technology – Contactless Deter-

mination of the Electrical Resistivity of Semi-Insulation

Semiconductor Slices using a Capacitive Probe

4 Terminology

4.1 Definitions

NOTE 1: The selected terminology defined here has been

adopted from ASTM Standard F1241. Updates to this section

are dependent on information exchange between ASTM and

SEMI. Definitions are included for the benefit of the user,

however, for a complete list, please refer to ASTM Standard

F1241.

4.1.1 bow (of a semiconductor wafer) — the deviation

of the center point of the median surface of a free,

unclamped wafer from a median-surface reference

plane established by three points equally spaced on a

circle with diameter a specified amount less than the

nominal diameter of the wafer. Contrast flatness. Also

see warp.

4.1.2 dopant — a chemical element, usually from the

second, fourth, or sixth column of the periodic table for

the case of III-V compounds, incorporated in trace

2 American Society for Quality Control, 611 East Wisconsin

Avenue, Milwaukee, WI 53202

3 Deutsches Institut fur Normung e.v., available from Beuth Verlag,

Burggrafenstrasse 6, D-10787 Berlin, Germany

amounts in a semiconductor crystal to establish its

conductivity type and resistivity.

4.1.3 edge profile — on wafers whose edges have been

rounded by mechanical and/or chemical means, a

description of the contour of the boundary of the wafer

that joins the front and back surfaces.

4.1.4 lot — for the purpose of this document, (a) all of

the wafers of nominally identical size and

characteristics contained in a single shipment, or (b)

subdivisions of large shipments consisting of wafers as

above which have been identified by the supplier as

constituting a lot.

4.1.5 orthogonal misorientation — in { 100} wafers cut

intentionally “off-orientation,” the angle between the

projection of the vector normal to the wafer surface

onto the { 100} plane and the projection on that plane of

the nearest direction (see Figure 5).

4.1.6 TIR — on a wafer surface, the smallest

perpendicular distance between two planes, both

parallel with the reference plane, which enclose all

points on the front surface of a wafer within the flatness

quality area or the site, depending on which is

specified.

4.1.7 TTV, total thickness variation — of a

semiconductor wafer, the difference between the

maximum and minimum values of the thickness of the

wafer.

4.1.8 warp — of a semiconductor wafer, the difference

between the maximum and minimum distances of the

median surface of a free, unclamped wafer from a

reference plane, encountered during a scan pattern.

5 Ordering Information

5.1 Purchase orders for indium phosphide wafers

furnished to this specification shall include the

following items:

5.1.1 Nominal diameter (see applicable SEMI Standard

for Polished InP wafers),

5.1.2 Thickness (see applicable SEMI Standard for

polished InP Wafers),

5.1.3 Total Thickness Variation, TIR, warp and bow

(determined by agreement between supplier and

purchaser as to limits),

5.1.4 Surface orientation (see applicable SEMI

Standard for polished InP wafers). There is only one

option of flat location for 2" diameter polished

monocrystalline InP wafers. The Dove-Tail option as

illustrated in Figures 1 and 3 is used for 2" diameter

InP. There is a choice of dovetail or V-Groove options

for 3" and 100mm diameter wafers. These designations