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SEMI G50-89 © SEMI 1989 2 seal area — A dimens ional outline area desi gnated f o r either m etallizatio n or base ceramic to provide a surface area for lid sealing (see Figure 2). terminal — Metallizatio n at the point …

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SEMI G50-89 © SEMI 19891
SEMI G50-89
SPECIFICATION FOR CO-FIRED CERAMIC FINE PITCH LEADED AND
LEADLESS CHIP CARRIER PACKAGE CONSTRUCTIONS
1 Preface
This specification defines the standard requirements for
co-fired ceramic fine pitch chip carrier constructions,
including both top brazed leaded and top metallized
leadless configurations. These constructions are for
hermetic packaging of various devices, (e.g., high
speed, digital VLSI silicon devices), and next-level
interconnection to printed wiring assemblies and
modules by either lead solder attachment or by “leads
last” techniques.
2 Applicable Documents
2.1 ANSI Specification
1
ANSI Y14.5 — Dimensioning and Tolerancing
2.2 Federal Specification
2
QQ-N-290 — Nickel Plating
2.3 JEDEC Specification
3
JEDEC Publication 95 — Registered and Standard
Outlines for Solid State Products
2.4 Military Specifications
MIL-STD-105 — Sampling Procedures and Tables for
Inspection by Attributes
MIL-STD-883 — Test Methods and Procedures for
Microelectronics
MIL-STD-7883 — Brazing
MIL-I-23011 — Iron Nickel Alloys for Sealing to Glass
and Ceramics
MIL-M-38510 — General Specification for
Microcircuits
MIL-G-45204 — Gold Plating, Electrodeposited
3 Selected Definitions
blister (bubble) — ceramics — Any separation within
the ceramic which does not expose underlying ceramic
material.
blister (bubble) — metal — Any localized separation
within the metallization or between the metallization
1 ANSI, 1430 Broadway, New York, NY 10018
2 Military Standards, Naval Publications and Form Center, 5801
Tabor Ave., Philadelphia, PA 19120
3 JEDEC, 2001 Eye Street, N.W., Washington, D.C. 20006
and ceramic which does not expose underlying metal or
ceramic material.
bond finger — A region of refractory metallization
within the package cavity intended for wirebonding to a
microcircuit die pad.
braze — An alloy with a melting point equal to or
greater than 600°C.
burr — An adherent fragment of excess parent material
at the component edge.
chip-out — A region of ceramic missing from the
surface or edge of a package which does not go
completely through the package. Chip-out size is given
by its length, width, and depth from a projection of the
design planform (see Figure 1).
co-fired — A process or technology for manufacturing
products in which the ceramic and refractory
metallization are fired simultaneously.
contact pad — That metallized pattern to which the
leadframe is brazed.
crack — A cleavage or fracture, internal or external.
die-attach surface — A designated dimensional outline
area intended for die attach (see Figure 1).
foreign material — An adherent particle other than
parent material of that component.
laver — A dielectric sheet with or without metallization
that performs a discrete function as part of the package
construction.
lead offset — Lead centerlines must be aligned to
within 0.254 mm (0.010") of the centerline of
corresponding braze pad metallizations.
peeling (flaking) — Any separation from the basis
material that exposes the basis material.
projection — An adherent fragment of excess material
on the component surface.
pullback — The linear distance between the edge of the
ceramic and the first measurable metallization surface
(see Figure 3).
rundown — The linear distance down a vertical surface
from the top to the point of maximum metallization
over-hand (see Figure 3).
SEMI G50-89 © SEMI 1989 2
seal area — A dimensional outline area designated for
either metallization or base ceramic to provide a surface
area for lid sealing (see Figure 2).
terminal — Metallization at the point of electrical
contact to package interior circuitry; also the brazing
surface for a lead.
TIR — Total indicator reading; the span of readings,
from minimum to maximum, of a given dimension over
the total surface it applied to.
voids (ceramics) — An absence of screen printed
ceramic from a designated area greater than 0.75 mm
(0.003") in diameter.
metal — An absence of refractory metallization, braze,
or plating material from a designated area greater than
0.075 mm (0.003") in diameter.
4 Ordering Information
4.1 Purchase orders for co-fired ceramic packaged
devices shall specify the following information:
1. Quantity
2. Drawing number and revision level or date
3. Reference to this specification
4. Any exception to drawing or specification
4.2 Drawings for co-fired ceramic packaged devices
shall specify the following information:
1. Drawing number and revision level
2. Number of terminals and terminal centerline
spacing
3. Lead material, finish, and dimensions, if applicable
4. Ceramic material color and composition; and
refractory metal type
5. Type and thickness of plating on both device body
and leads, if applicable
6. Dimensioning and tolerancing per ANSI Y14.5
7. Internal bonding pattern
8. Lead number 1 position
9. Method of test and measurements
10.Electrical, mechanical, and environmental
requirements
5 Dimensions and Permissi ble Variations
Packaged device dimensions shall conform to JEDEC
JC-11 registered outline dimension drawings for co-
fired ceramic fine pitch leaded and leadless chip
carriers, unless otherwise specified.
6 Materials
6.1 Ceramic
6.1.1 Alumina content to be 90% minimum. Beryllia
content to be 99% minimum.
6.1.2 Color to be black, dark brown, or dark violet
unless otherwise specified.
6.2 Metals — External metal surfaces shall be in
accordance with MIL-M-38510.
6.3 Braze — Copper/silver per MIL-STD-7883.
6.4 Refractory Metallization — To be per MIL-M-
38510, Type C.
6.5 Leadframe — Fully annealed iron nickel cobalt
alloy (per MIL-M-38410, Type A) or iron nickel alloy
(per MIL-M-38510, Type B).
6.6 Microcircuit Finishes — Shall be per MlL-M-
38510 unless otherwise specified.
7 Incoming Test Sequence
1. Visual inspection
2. Dimensional check
3. Electrical parameter testing
4. Sampling testing of plating quality, die attach, die
shear, wire bond, pull, seal, hermeticity, lead
integrity, and solderability
8 Visual Criteria (10× Magni fication)
8.1 Cracks — None allowed per MIL-STD-883,
Method 2009.
8.2 Chips
8.2.1 Corner — 0.762 mm (0.030") × 0.762 mm
(0.030") × one tape layer thickness, maximum.
8.2.2 Edge — 0.54 mm (0.100") × 0.762 mm (0.030")
× one tape layer thickness, maximum.
8.3 Burrs, Projections, and Blisters — Must fit within
outline limit.
Top plane excluding seal area — 0.102 mm
(0.004"), maximum
Unmetallized seal area — 0.0762 mm (0.003"),
maximum
Metallized seal area — 0.025 mm (0.001"),
maximum
SEMI G50-89 © SEMI 19893
Bottom surface — 0.051 mm (0.002"), maximum
Edges — 0.152 mm (0.006"), maximum
Terminal pads — 0.051 mm (0.002"), maximum
Wire bond fingers — 0.025 mm (0.001"), maximum
Die attach surface — 0.025 mm (0.001"), maximum
8.4 Camber — 0.004" inch/inch (mm/mm), maximum.
For dimensions less than 10.05 mm (0.750"), 0.127 mm
(0.003") camber is permitted along any planar
dimension of the device package.
8.5 Seal Area Flatness — The seal area shall be flat
within the limits listed in Table l.
8.6 Die Attach Surface Flatness — The die attach
surface shall be flat within the limits listed in Table 2.
Table 1 Seal Ring Flatness Limits
Seal Ring OD Ring Flatness
0–0.250" (0–6.35 mm) 0.002" max. (0.051 mm)
0.251"–0.550" (6.37–13.97 mm) 0.003" max. (0.076 mm)
0.501"–1.000" (12.7–25.40 mm) 0.004" max. (0.101 mm)
> 1.000" (> 25.40 mm) 0.004"/inch (0.101 mm/mm)
Table 2 Die Attach Area Flatness Limits
Die Attach Pad Dimension TIR Flatness
0–0.500" (0–12.7 mm) 0.002" max. (0.051 mm)
0.501"–0.750" (12.7–19.5 mm) 0.003" max. (0.076 mm)
8.7 Voids
8.7.1 Seal Area Void — A maximum of three voids
permitted. Not more than two voids per side of 0.010"
diameter. Any two voids must be separated by 0.762
mm (0.010") minimum, not to degrade the seal width
by more than 25%.
8.7.2 Terminal Void — A maximum of two voids per
terminal pad permissible. Maximum void diameter
acceptable is 0.127 mm (0.005"). Voids may never
reduce the minimum terminal width to less than two-
thirds of the nominal design dimension.
8.7.3 Wire Bond Finger Void — Void free 0.015"
back from the bond finger tip.
8.7.4 Die Attach Surface Voids — Three voids of
0.010" diameter are the maximum allowed separated by
0.030" minimum.
NOTE: Voids within 0.015" of the cavity wall not included.
8.7.5 Internal Metallization Voids — Voids in internal
metallization planes or traces shall not break continuity.
Specific requirements for resistance and capacitance
parameters shall be specified in the purchase order, if
applicable.
8.8 Pattern Metallizations
8.8.1 Seal Plane Rundown (internal cavity) — Not to
exceed 25% of the cavity layer thickness.
8.8.2 Seal Plane Rundown (external to cavity) — Not
to exceed half the nominal design distance to adjacent
edge metallization. In no event shall the rundown be
closer than 0.254 mm (0.010") to any edge
metalization.
8.8.3 Wire Bond Rundown — Wire bond finger
rundown shall not exceed 25% of the cavity depth or
0.127 mm (0.005"), whichever is smaller.
8.8.4 Wire Bond Finger Pullback — Wire bond finger
pullback shall not exceed 0.127 mm (0.005") from the
nominal design dimension for finger end to cavity edge.
8.8.5 Seal Plane Pullback — Seal plane pullback shall
not exceed 0.127 mm (0.005") from the nominal design
dimension for seal plane metallization to edge.
8.9 Lead Attachment (when applicable)
8.9.1 Voids in Braze — Braze fillets must be 95% free
of voids.
8.9.2 Lead Alignment — Brazed leads shall not
overhang braze pads.
8.9.3 Lead Offset — Lead centerlines must be aligned
to within 0.0762 mm (0.003") of the centerlines of
corresponding braze pad metallizations.
8.9.4 Lead-to-Lead Misalignment — Not to exceed
10% of nominal spacing.
8.9.5 Dimensional Criteria — Per JEDEC JC-11
registered outline drawings in JEDEC Publication 95,
or as specified on the user drawings.
9 Sampling
Sample sizes must meet requirements of MIL-STD-105
or MIL-M-38510 as agreed to between vendor and
customer.
10 Test Methods (Mechanical, Electrical, and
Thermal)
10.1 Gold Plating Thickness — Shall conform to
MIL-G-45204. Gold thickness may be determined
using the Beta Backscatter Radiation Method or x-ray
fluorescence.
10.2 Nickel Plating — Shall conform to QQ-N-290.
Nickel thickness may be determined using the Beta
Backscatter Radiation Method or x-ray fluorescence.