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SEMI G39-89 © SEMI 198 6, 1989 4 using th e B eta Backscatter Radiation Method, X-R a y Fluores cence or by Cros s Sectioni ng. 10.2 N ickel Plating — Shall conf or m t o QQ-N-290. Nickel thickness m a y be determined us…

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SEMI G39-89 © SEMI 1986, 19893
8.3.3 Metallized Seal Area — 0.025 mm (0.001"),
maximum.
8.3.4 Bottom Surface — 0.051 mm (0.002"),
maximum.
8.3.5 Edges — 0.152 mm (0.006"), maximum.
8.3.6 Terminal Pads — 0.051 mm (0.002"),
maximum.
8.3.7 Wire Bond Fingers — 0.025 mm (0.001"),
maximum.
8.3.8 Die Attach Surface Flatness — 0.025 mm
(0.001"), maximum.
8.4 Camber — .004 inch/inch (mm/mm), maximum.
For dimensions less than 10.5 mm (0.750"), 0.127 mm
(0.003") camber is permitted along any planar
dimension of the device package.
8.5 Seal Area Flatness — The seal area shall be within
the limits listed in Table 1.
8.6 Die Attach Surface Flatness — The die attach
surface shall be flat within the limits listed in Table 2.
Table 1 Seal Ring Flatness Limits
Seal Ring O.D. Seal Ring Flatness
0—6.35 mm (0–0.250") 0.051 mm max. (0.002")
6.37—12.7 mm (0.251"–0.500") 0.051 mm max. (0.002")
12.72—25.40 mm (0.501"–
1.000")
0.101 mm max. (0.004")
25.40 mm (1.000") 0.101 mm/mm (0.004"/in.)
Table 2 Die Attach Area Flatness Limits
Die Attach Pad Dimension TIR Flatness
0—12.7 mm (0—0.500") 0.051 mm max. (0.002")
12.72—19.5 mm (0.501"—0.750") 0.088 mm max. (0.0035")
8.7 Voids
8.7.1 Seal Area Voids — A maximum of 3 voids
permitted. Not more than two voids per side of 0.010"
diameter. Any two voids must be separated by 0.762
mm (0.030") minimum, not to degrade the seal width
by more than 25%.
8.7.2 Terminal Void — A maximum of two voids per
terminal pad permissible. Maximum void diameter
acceptable is 0.254 mm (0.101). Voids may never
reduce the minimum terminal width to less than 2/3 of
the nominal design dimension.
8.7.3 Wire Bond Finger Voids — Void free 0.015"
back from the bond finger tip.
8.7.4 Die Attach Surface Voids — Three voids of
0.010" diameter are the maximum allowed separated by
0.030" minimum.
NOTE — Voids 0.015" from the cavity wall not included.
8.7.5 Internal Metallization Voids — Voids in internal
metallization planes or traces shall not break continuity.
Specific requirements for resistance and capacitance
parameters shall be specified in the purchase order, if
applicable.
8.8 Pattern Metallizations
8.8.1 Seal Plan Rundown (internal cavity) — Not to
exceed 25% of the cavity layer thickness.
8.8.2 Seal Plan Rundown (external to cavity) — Not
to exceed half the nominal design distance to adjacent
edge metallization. In no event shall the rundown be
closer than 0.254 mm (0.010") to any edge
metallization.
8.8.3 Wire Bond Rundown — Wire bond finger
rundown shall not exceed 25% of the cavity depth or
0.005" (0.127 mm) whichever is smaller.
8.8.4 Wire Bond Finger Pullback — Wire bond finger
pullback shall not exceed 0.127 mm (0.005") from the
nominal design dimension for finger end to cavity edge.
8.8.5 Seal Plane Pullback — Seal plane pullback shall
not exceed 0.127 mm (0.005") from the nominal design
dimension for seal plane metallization to edge.
8.9 Lead Attachment
8.9.1 Voids in Braze — Braze fillets must be 95% free
of voids, shall not cause voids under a lead.
8.9.2 Lead Offset — Lead centerlines must be aligned
to within 0.127 mm (0.005") of the centerlines of
corresponding braze pad metallizations. Side to side
within 0.010".
8.9.3 Lead-to-Lead Misalignment — To exceed 10%
of nominal spacing.
8.9.4 Dimensional Criteria — Per JEDEC JC-11
registered outline drawings in JEDEC Publication 95,
or as specified on the user drawings.
9 Sampling
Sample size must meet requirements of MIL-STD-105
or MIL-M-38510 as agreed to between user and
supplier.
10 Test Methods (Mechanical, Electrical, and
Thermal)
10.1 Gold Plating Thickness — Shall conform to
MIL-STD-45204. Gold thickness may be determined
SEMI G39-89 © SEMI 1986, 1989 4
using the Beta Backscatter Radiation Method, X-Ray
Fluorescence or by Cross Sectioning.
10.2 Nickel Plating — Shall conform to QQ-N-290.
Nickel thickness may be determined using the Beta
Backscatter Radiation Method, X-Ray Fluorescence, or
by Cross Sectioning.
10.3 Destructive Die Shear Testing — Shall be
performed per Method 2019 of MIL-STD-883.
10.4 Wire Bond Pull Testing — Shall be performed
per Method 2011, Condition D of MIL-STD-883.
10.5 Temperature Cycling Testing — Shall be
performed per Method 1010, Condition C of MIL-STD-
883.
10.6 Thermal Shock Testing — Shall be performed per
Method 1011, Condition C of MIL-STD-883.
10.7 Constant Acceleration Testing — Shall be
performed per Method 2001, Condition E, Y axis only,
of MIL-STD-883.
10.8 Mechanical Shock Testing — Shall be performed
per Method 2002, Condition B of MIL-STD-883.
10.9 Insulation Resistance Testing — Shall be
performed per Method 1003 of MIL-STD-883.
10.10 Internal Water Vapor Content Testing — Shall
be performed per Method 1018 of MIL-STD-883.
10.11 Hermeticity Testing — Shall be performed per
Method 1014, Condition A of MIL-STD-883. The
hermetic integrity of the packaged device must be
maintained after all testing.
10.12 Lead Integrity Testing — Shall be performed
per Method 2004, Condition A, B1, and B2 of MIL-
STD-883.
10.13 Solderability Testing — Shall be performed per
Method 2003 of MIL-STD-883.
10.14 Moisture Resistance Testing — Shall be
performed per Method 1004 of MIL-STD-883.
11 Packaging and Marking
11.1 Packaging — Containers selected shall be strong
enough and suitably designed to provide maximum
protection against crushing, spillage and other forms of
damage to the container or its contents. Container shall
afford protection of the contents to contamination from
exposure to excessive moisture or oxidation by gases.
Packaging material shall be so selected to prevent any
contamination of the ceramic component parts with
fibers or organic particles.
11.2 Marking — The outer containers shall be clearly
marked identifying:
1. Supplier part number.
2. User part number.
3. Quantity.
4. Date of manufacture.
5. Supplier lot number.
12 Applicability
This specification is intended to apply to construction
utilizing the tall brazed lead flatpack outlines included
in JEDEC Publication 95.
Figure 1
Chip Illustration
Figure 2
Die Attach Surface and Seal Area
SEMI G39-89 © SEMI 1986, 19895
Figure 3
Metallization Misalignment
NOTICE: These standards do not purport to address
safety issues, if any, associated with their use. It is the
responsibility of the user of these standards to establish
appropriate safety and health practices and determine
the applicability of regulatory limitations prior to use.
SEMI makes no warranties or representations as to the
suitability of the standards set forth herein for any
particular application. The determination of the
suitability of the standard is solely the responsibility of
the user. Users are cautioned to refer to manufacturer’s
instructions, product labels, product data sheets, and
other relevant literature respecting any materials
mentioned herein. These standards are subject to
change without notice.
The user’s attention is called to the possibility that
compliance with this standard may require use of
copyrighted material or of an invention covered by
patent rights. By publication of this standard, SEMI
takes no position respecting the validity of any patent
rights or copyrights asserted in connection with any
item mentioned in this standard. Users of this standard
are expressly advised that determination of any such
patent rights or copyrights, and the risk of infringement
of such rights, are entirely their own responsibility.
Copyright by SEMI® (Semiconductor Equipment and Materials
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