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SEMI M46-1101 E © SEMI 2001 6 Where C excess is the capacitance of material in the excess area, A w is the w etted area, A i is the illum inated area 13.2 Depletion Dept h , W d , — calculated from the parallel plate cap…

SEMI M46-1101

12.4 Contact Evaluation — Verify that the contacts,

for both directions of current flow have low and

approximately equal resistance.

12.5 Rest Potential — Measure the sample’s rest

potential to verify that the reference electrode and

sample are electrochemically stable. Its value usually

lies between 0 and −1 V (respective to a SCE reference

electrode). Values outside this range can indicate a

problem with the sample or reference electrode.

12.6 Cable Compensation — Determine any stray

capacitance or additional resistance associated with the

cell and test leads that would impact the measurement.

12.7 Current vs. Voltage (I-V) — Used to select the

bias for measurement and etching and as a general test

of material quality.

12.7.1 Measurement Bias — is set in the reverse bias,

low dark current region.

12.7.2 Etching Bias (p-type material) — is set in the

forward bias region. The abruptness of the forward bias

breakdown is indicative of the ohmic nature of the

contacts. No or shallow forward breakdown often

indicates unsuitable ohmic contacts.

12.7.3 Etching Bias (n-type material) — is set in the

reverse bias, low dark current region. Illumination

should result in a significant increase in current (photo-

current).

12.8 Capacitance vs. Voltage (C-V) — Used to

evaluate the quality of the electrochemical diode and to

select a range of possible measurement voltages. The

measured flatband potential (respective to a SCE

reference electrode) should lie between −0.5 and

−2.5 V for n-type semiconductors and between –1 and

+1 V for p-type semiconductors.

12.8.1 Measurement Bias — is set in a region of low

dissipation, where the 1/C

vs V plot is linear. For

layers grown with concentration gradients, the latter

condition cannot be strictly adhered to and in such

cases the amplitude of the test signal, used for

capacitance measurement, should be kept as small as

possible.

12.8.2 Dissipation — The normally accepted safe level

is < 0.4.

12.8.3 Excess Area Capacitance — For n-type surface

layers the capacitance of the electrolyte/semiconductor

interface is measured prior to etching and the

capacitance associated with the excess area is computed

by multiplying the measured capacitance by the ratio of

the excess area to the wetted area.

12.9 Carrier Concentration Profiling — Profile the

sample using the etching and measurement conditions

determined from the I-V and C-V data.

12.9.1 Carrier Concentration — The carrier

concentration is determined from the C-V data.

12.9.2 Excess Area Correction — For n-type material

the capacitance associated with material in the excess

area should be subtracted from the measured

capacitance.

12.9.3 Etching — The sample is anodically etched at

the etching bias. The depth of the etch well is

determined from the time integral of the current using

Faraday’s law of electrolysis.

12.9.4 Profiled Depth — The profile assumes that the

measured carrier concentration lies at a depth equal to

the sum of the etch and the depletion depths.

12.10 Ring Area — It is advised to measure the etch

well area after profiling and to use this value to

recalculate the carrier concentration vs. depth profile.

13 Calculations and Interpretation of Results

13.1 Carrier Concentration, N

The principle of this method is based on measuring the

slope of 1/C

vs V.

()

−

εε

[cm

-3

]

where

C is the measured capacitance (for n-type

material the capacitance associated with the

excess area should be subtracted from the

measured capacitance),

V is the applied bias,

q is the electronic charge,

is the relative permittivity of the sample,

is the permittivity of free space

(= 8.854 × 10

-12

-1

)

A is the area of the etch well

It is also possible to measure dC/dV by modulating the

bias with a low frequency (secondary signal). The

d(1/C

)/dV of the upper equation may be evaluated to

result in the following formula.

εε

[cm

-3

]

13.1.1 Excess Area Capacitance, excessC

excess

−

= .

[F]

SEMI M46-1101

Where

excess

is the capacitance of material in the

excess area,

is the wetted area,

is the illuminated area

13.2 Depletion Depth, W

, — calculated from the

parallel plate capacitor equation.

[µm]

13.3 Etched depth, W

— calculated from the charged

passed through the cell using Faraday’s law for

electrolysis.

FDA

Idte =

[µm]

Where

z is the effective dissolution valency,

F is the Faraday constant,

(= 9.65 × 10

Cmol

-1

)

D is the density of the semiconductor,

M is the molecular weight of the

semiconductor

I is the etch current

13.4 Total depth, W, — the sum of the depletion and

etch depths and is the depth at which the measurement

is made.

de=+ [µm]

14 Reporting Results

14.1 The following information shall be included in the

report:

14.1.1 Identification of Specimen — including details

of any pretreatment such as the use of a selective etch

to chemically etch the sample to the layer of interest.

14.1.2 Sealing Ring Area — both the wetted and

illuminated areas should be reported.

14.1.3 Electrolyte — the composition of the electrolyte

should specify the molecular concentration.

14.1.4 Material Constants — The relative permittivity

of the sample,

and the effective dissolution valency,

14.1.5 Primary Measurement Signal — the frequency

and amplitude of the signal used for the capacitance

measurement.

14.1.6 Secondary (bias) Signal — If the measurement

is made using a secondary modulation component its

frequency and amplitude should be reported. If the

measurement is made by changing the bias, its

minimum and maximum value should be specified.

14.1.7 Measurement Bias — The average value (DC

component) of the bias used during the capacitance

measurement.

14.1.8 Electrochemical Etching Bias — The bias used

to etch the sample including whether or not the sample

was illuminated. If etched at a constant current this

should be stated. Then it is not necessary to report the

bias.

14.1.9 Electrochemical Etching Current — If etched at

constant bias the average value of current measured

during electrochemical etching. If etched at a constant

current the value used.

NOTICE:. SEMI makes no warranties or

representations as to the suitability of the standards set

forth herein for any particular application. The

determination of the suitability of the standard is solely

the responsibility of the user. Users are cautioned to

refer to manufacturer’s instructions, product labels,

product data sheets, and other relevant literature

respecting any materials mentioned herein. These

standards are subject to change without notice.

The user’s attention is called to the possibility that

compliance with this standard may require use of

copyrighted material or of an invention covered by

patent rights. By publication of this standard, SEMI

takes no position respecting the validity of any patent

rights or copyrights asserted in connection with any

item mentioned in this standard. Users of this standard

are expressly advised that determination of any such

patent rights or copyrights, and the risk of infringement

of such rights, are entirely their own responsibility.

International), 3081 Zanker Road, San Jose, CA 95134. Reproduction o

the contents in whole or in part is forbidden without express writte

consent of SEMI.

SEMI M47-0704

SPECIFICATION FOR SILICON-ON-INSULATOR (SOI) WAFERS FOR

CMOS LSI APPLICATIONS

This specification technically approved by the Global Silicon Wafer Committee and is the direct

responsibility of the Japanese Silicon Wafer Committee. Current edition approved by the Japanese Regional

Standards Committee on April 30, 2004. Initially available at www.semi.org June 2004; to be published July

2004. Originally published November 2001; previously published March 2002.

1 Purpose

1.1 This specification defines thin-layer silicon-on-

insulator (SOI) wafer requirements for CMOS large

scale integrated circuit (LSI) devices. In another aspect,

this specification defines the generic characteristics of

SIMOX and bonded silicon-on-insulator wafers having

typically no more than 0.2 µm SOI layer thickness. By

defining parameters, inspection procedures and

acceptance criteria, both users and suppliers may

uniformly define product characteristics and quality

requirements.

2 Scope

2.1 This specification is specifically directed to

SIMOX and bonded silicon-on-insulator wafers, which

are exclusively used for LSI applications made up of

CMOS devices.

2.2 A complete purchase specification requires the

base silicon wafer, SOI surface and layer, and buried

oxide layer properties detailed in this standard, suitable

test methods for their characterization. SEMI M18 may

be for purchase specification purpose.

NOTICE: This standard does not purport to address

safety issues, if any, associated with its use. It is the

responsibility of the users of this standard to establish

appropriate safety and health practices and determine

the applicability of regulatory or other limitations prior

to use.

3 Referenced Standards

3.1 SEMI Standards

SEMI M1 — Specifications for Polished

Monocrystalline Silicon Wafers

SEMI M11 — Specifications for Silicon Epitaxial

Wafers for Integrated Circuit (IC) Applications

SEMI M18 — Format for Silicon Wafer Specification

From for Order Entry

SEMI M22 — Specifications for Dielectrically Isolated

(DI) Wafers

SEMI M34 — Guide for Specifying SIMOX Wafers

SEMI M35 — Guide for Developing Specifications for

Silicon Wafer Surface Features Detected by Automated

Inspection

SEMI M41 — Specification of Silicon-on Insulator

(SOI) for Power Device/ICs

SEMI MF26 — Standard Test Methods for

Determining the Orientation of a Semiconductive

Single Crystal

SEMI MF42 — Standard Test Methods for

Conductivity Type of Extrinsic Semiconductor

Materials

SEMI MF84 — Standard Test Method for Measuring

Resistivity of Silicon Wafers with an In-Line Four-

Point Probe

SEMI MF523 — Standard Practice for Unaided Visual

Inspection of Polished Silicon Wafer Surfaces

SEMI MF533 — Standard Test Method for Thickness

and Thickness Variation of Silicon Wafers

SEMI MF671 — Standard Test Method for Measuring

Flat Length on Wafers of Silicon and Other Electronic

Materials

SEMI MF928 — Standard Test Methods for Edge

Contour of Circular Semiconductor Wafers and Rigid

Disk Substrates

SEMI MF1152 — Standard Test Methods for

Dimensions of Notches on Silicon Wafers

SEMI MF1188 — Standard Test Method for Interstitial

Atomic Oxygen Content of Silicon by Infrared

Absorption

SEMI MF1241 — Standard Test Methods for

Terminology of Silicon Technology

SEMI MF1390 — Standard Test Method for Measuring

Warp on Silicon Wafers by Automated Noncontact

Scanning

SEMI MF1526 — Standard Test Method for Measuring

Surface Metal Contamination on Silicon Wafers by

Total Reflection X-Ray Fluorescence Spectroscopy