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SEMI M55-0705 © SEMI 2003, 2004 7 NOTE 11: For microscopic inspection th e use of crossed polarisers is recommended. However not al l micropipes will be visible under crossed polarisers. 10.3.4 planar defect — Any anomal…

SEMI M55-0705 © SEMI 2003, 2004 6

NOTE 8: ASTM F43 is a four-point-probe technique whereas ASTM F673 is an inductive non-contact method. These methods

are limited to some 10

cm. DIN 50448 is a non-contact capacitive method suitable for the range 10

to 10

cm.

8.15 Etch Pit Density  Determine by ASTM Test Method F1404 or a method agreed upon between the supplier

and purchaser.

NOTE 9: ASTM test method F1404 was intended only for use with gallium arsenide. Nevertheless it should serve as a guideline

for determining the etch pit density of silicon carbide.

8.16 Micropipe Density  Determine by a method agreed upon between the supplier and purchaser.

8.17 Crystal Perfection  Determine by a method agreed upon between the supplier and purchaser.

9 Flat System

9.1 For silicon carbide wafers with the surface normal close to the crystallographic c-axis (small tilt angles, see

Figure 2) one primary orientation flat and one secondary flat is specified. The primary flat always has a greater flat

length compared to the secondary flat. (See Figure 6.)

9.2 The angle between primary and secondary flat is always 90° (see Figure 5). For the tolerance see the

appropriate silicon carbide wafer standard.

9.3 The polarity of the wafer surfaces is indicated by the relative flat positions of primary and secondary flat as

shown in Figure 5.

9.4 The edge of the primary flat is always parallel to the [11-20] direction (or, which is the same, parallel to the (1-

100) lattice plane.) For tolerances see the appropriate silicon carbide wafer standard.

9.5 For the exact dimensions of the flat length and the tolerances see the appropriate silicon carbide wafer standard.

10 Standard Defect Limits

10.1 Minimal conditions or dimensions for surface defects are stated below. These limits shall be used for

determining wafer acceptability; anomalies smaller than these limits shall not be considered as defects.

10.2 Surface Defects

10.2.1 edge chip and indent — Any edge anomaly including saw exit marks conforming to the definition (ASTM

F154) and greater than 0.25 mm in radial depth and peripheral length. (See Figure 7.)

10.2.2 orange peel — Any visually detectable roughened surface conforming to the definition (ASTM F154) and

observable under diffused illumination. Pits with a spacing of less than 2 mm are treated as orange peel.

10.2.3 particles — Distinct particles resting on the surface which are revealed under collimated intense light as

bright points.

10.2.4 pit — Any individually distinguishable depression in the surface with a length-to-width ratio smaller than

5:1, visible when viewed under intense illumination.

NOTE 10: This definition is different from ASTM F154 in so far as the slope of the sides of the depression are not taken into

account.

10.2.5 scratch — Any anomaly conforming to the definition (ASTM F154) and having a length-to-width ratio

greater than 5:1 and visible under intense illumination.

10.3 Bulk Defects

10.3.1 crack — Any anomaly conforming to the definition (ASTM F154) and greater than 0.25 mm in total length.

10.3.2 crystallite — Any anomaly conforming to the definition (see §3) and having a misorientation of more than

1° to the main (monocrystalline) part of the wafer and having a maximum width larger than 0.20 mm.

10.3.3 micropipe — Any anomaly conforming to the definition (see §3) and visible by microscopic inspection in

transmission mode at a magnification of 100× or after etching in molten KOH, which will reveal micropipes as

hexagonal structures.

SEMI M55-0705 © SEMI 2003, 2004 7

NOTE 11: For microscopic inspection the use of crossed polarisers is recommended. However not all micropipes will be visible

under crossed polarisers.

10.3.4 planar defect — Any anomaly conforming to the definition (see §3) having a maximum width larger than

0.20 mm.

11 Certification

11.1 Upon request of the purchaser in the contract or order, a manufacturer’s or supplier’s certification that the

material was manufactured and tested in accordance with this specification together, with a report of the test results,

shall be furnished at the time of shipment.

11.2 In the interest of controlling inspection costs, the supplier and the purchaser may agree that the material shall

be certified as “capable of meeting” certain requirements. In this context, “capable of meeting” shall signify that the

supplier is not required to perform the appropriate tests in §8. However, if the purchaser performs the test and the

material fails to meet the requirement, the material may be subject to rejection.

12 Packing and Marking

12.1 The wafers supplied under these specifications shall be identified by an individual laser marking consisting of

the supplier assigned lot-number on the backside of each wafer. The laser marking consists of one line of characters

parallel to the primary flat and must be readable with unaided eye. The top of the characters is directed towards the

wafer center. All characters must be completely located within the marking window given in Figure 8. For details

see the appropriate polished Silicon Carbide Wafer Standard.

NOTE 12: SEMI M12 is a standard for the front side marking of silicon wafers and, as a whole, is not applicable to Silicon

Carbide wafers. It is referenced, because some elements of SEMI M12 (see the appropriate polished Silicon Carbide Wafer

Standard) shall also be used for Silicon Carbide.

12.2 Special packing and marking requirements shall be subject to agreement between the supplier and the

purchaser. Otherwise, all wafers shall be handled, inspected, and packed in such a manner as to avoid chipping,

scratches, and contamination in accordance with the best industry practices to provide ample protection against

damage during shipment.

12.3 The wafers shall be identified by appropriately labeling the outside of each box or other container and each

subdivision thereof in which it may reasonably be expected that the wafers will be stored prior to further processing.

Identification shall include as a minimum the nominal diameter, conductive dopant, orientation, resistivity range,

and lot number.

12.4 The lot number, either (1) assigned by the original manufacturer of the wafers, or (2) assigned subsequent to

slice manufacture but providing reference to the original lot number, shall provide easy access to information

concerning the fabrication history of the particular wafers in that lot. Such information shall be retained on file at

the manufacturer's facility for at least 10 years or as negotiated between vendor and user after that particular lot has

been accepted by the purchaser.

13 Related Documents

13.1 ASTM Standards

ASTM F76  Test Methods for Measuring Resistivity and Hall Coefficient and Determining Hall Mobility in

Single-Crystal Semiconductors

ASTM F1241  Terminology of Silicon Technology

13.2 DIN-Standards

DIN 50433/1 — Determination of the Orientation of Single Crystals by Means of X-Ray Diffraction

DIN 50433/3 — Determination of the Orientation of Single Crystals by Means of Laue Back Scattering

DIN 50441/2 — Measurement of the Geometric Dimensions of Semiconductor Wafers: Testing of Edge Profile

DIN 50441/4 — Measurement of the Geometrical Dimensions of Semiconductor Wafers: Slice Diameter, Diameter

Variation, Flat Diameter, Flat Length, Flat Depth

DIN 50445 — Testing of materials for semiconductor technology; Contactless determination of the electrical

resistivity of semiconductor slices with the eddy current method; Homogeneously doped semiconductor wafers

13.3 ISO Standards

ISO 4287 — Geometrical Product Specifications (GPS) -- Surface texture: Profile method -- Terms, definitions and

surface texture parameters

Primary Flat

Secondary Flat

Wafer Periphery

Fixed Quality Area Boundary

X = Nominal Edge Exlusion

Figure 1

Fixed Quality Area

Vector Normal to

Wafer Surface

Orthogonal

Misorientation

Crystallographic c-Axis

<0001>

Tilt Angle

{0001} -Plane

Projection of Wafer Surface Normal

on the {0001} -Plane

Specified Direction of Tilt

(in {0001} -Plane)

Tilt Angle

{0001} Plane

Wafer

Figure 2

Orthogonal Misorientation

7 International Organization for Standardization, ISO Central Secretariat, 1, rue de Varembé, Case postale 56, CH-1211 Geneva 20, Switzerland.

Telephone: 41.22.749.01.11; Fax: 41.22.733.34.30 Website: www.iso.ch