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SEMI G1-96 © SEMI 1 980, 199 6 2 5.3 camber (ceramic) — Arc hing o f a no minal ly flat ceramic body . 5.4 chip — A regi on of material m i s si ng from a compon e nt (e.g ., cera mic from a package, or solder from a pre…
SEMI G1-96 © SEMI 1980, 19961
SEMI G1-96
SPECIFICATION FOR CERDIP PACKAGE CONSTRUCTIONS
NOTE: This entire document was revised in 1996.
1 Purpose
This specification defines the materials and acceptance
criteria for the components (bases, window frames, and
caps) or sub-assemblies (leadframes mounted in a
sandwich between bases and window frames) used for
cerdip package constructions.
NOTE 1: Materials and acceptance criteria for leadframes,
purchased separately for these constructions, are described in
SEMI G2.
2 Scope
This specification applies to all cerdip (dual-in-line)
packages which have either:
• A leadframe sandwiched between two ceramic
pieces — the base and a window frame — and
sealed by a solder glass layer, and a cap with a
similar seal; or,
• A leadframe mounted into a solder glass layer on a
ceramic base, and a cap with a similar glass seal
layer.
NOTE 2: The base, leadframe, and, if required, the window
frame may be purchased as separate components or as a sub-
assembly.
3 Units
This specification uses U.S. Customary (inch pound)
units as the prime unit.
4 Referenced Documents
4.1 Order of Precedence
To avoid conflicts, the order of precedence when
ordering components or sub-assemblies for cerdip
packages shall be as follows:
• Purchase order
• User’s package drawings
• This specification
• Reference documents
• Related documents
4.2 Referenced Documents
4.3 SEMI Specifications
SEMI G2 — Specification Metallic Leadframes for
Cer-Dip Packages
SEMI G20 — Specification Lead Finishes for Plastic
Packages (Active Devices only)
SEMI G23 — Test Method Measuring the Inductance
of Package Leads
SEMI G24 — Test Method Measuring the Lead-to-
Lead and Loading Capacitance of Package Leads
SEMI G25 — Test Method Measuring the Resistance
of Package Leads
SEMI G30 — Test Method Junction-to-Case Thermal
Resistance Measurements of Ceramic Packages
4.4 ANSI Specification
1
ANSI Y14.5M — Dimensioning and Tolerancing
4.5 JEDEC Publication
2
JEDEC Publication 95 — Registered and Standard
Outlines for Semiconductor Devices
4.6 Military and Federal Specifications
3
MIL-STD-105D — Sampling Procedures and Tables
for Inspection by Attributes
MIL-STD-883 — Test Methods and Procedures for
Microelectronics
MIL-STD-1835 — Microcircuit Case Outlines
MIL-I-38535 — General Specifications for
Microcircuits
5 Terminology
5.1 blister (bubble) metallization — An enclosed,
localized separation of the metallization from its base
material (such as ceramic or other metallization layer
component) that does not expose the underlying layer.
5.2 burr — An adherent fragment of parent material at
a component edge. In leadframes, the metal burr, due to
the stamping operation, may be in the horizontal or
vertical direction to the surface. In ceramic packages,
this type of characteristic is called a fin.
1 American National Standards Institute, 1430 Broadway, New York,
NY 10018
2 Joint Electronic Development Engineering Council, 2001 Eye
Street, N.W., Washington, D.C. 20006
3 Military Standards, Naval Publications and Form Center, 5801
Tabor Avenue, Philadelphia, PA 19120
SEMI G1-96 © SEMI 1980, 1996 2
5.3 camber (ceramic) — Arching of a nominally flat
ceramic body.
5.4 chip — A region of material missing from a
component (e.g., ceramic from a package, or solder
from a preform). The region does not progress
completely through the component and is formed after
the component is manufactured. Chip size is defined by
its length, width, and depth from a projection of the
design planform. Also called chipout (see Figure 1).
Figure 1
5.5 crack — A cleavage or fracture that extends to the
surface of a semiconductor package or solder
preform.The crack may or may not pass through the
entire thickness of the package or preform.
5.6 critical seal area — On a semiconductor package,
the area bounded by the shortest nominal design
distance from the largest cavity, usually the wire bond
cavity, to the edge of the package or ceramic layer
forming the seal area (see Figure 2).
Figure 2
Critical and Non-Critical Seal Area
5.7 fin — On a ceramic package or cap, a fine
feathery-edged projection of parent ceramic material on
the corner of the ceramic body.
5.8 foreign material — An adherent particle that is not
parent material of the component. Adherence means
that the particle cannot be removed by an air or nitrogen
blast at 20 psi.
5.9 glass flow — On a semiconductor package or cap,
the heating process which just removes all the screen
printing mesh marks in the sealing glass when viewed
at 10× magnification.
5.10 glass void — The absence of a sealing glass layer
from a designated area.
5.11 metallization void — The absence of a clad,
evaporated, plated, or screen-printed metal layer or
braze from a designated area.
5.12 non-critical seal area — On a semiconductor
package that uses a lid, cap, or cover to effect the seal,
the area of the sealing surface outside the critical
sealing area (see Figure 2).
5.13 overhang — On a semiconductor package, the
horizontal extension of the sealing glass past the
vertical wall of a cavity cut into the ceramic layer on
which the glass is printed (see Figure 3).
Figure 3
Glass Misalignment
5.14 peeling (flaking) — Any separation of a plated,
vacuum-deposited, or clad metal layer from the base
metal of a leadframe, pin heatsink, or seal ring, from an
underplate or from a refractory metal on a ceramic
package. Peeling exposes the underlying metal.
5.15 projection — On a semiconductor package
(plastic or ceramic) leadframe or preform, an irregularly
raised portion of a surface indigenous to the parent
material.
5.16 pullback — On a semiconductor package, the
linear distance between the edge of a cavity cut into a
ceramic layer and the first measurable glass or
metallization layer interface coated onto the top surface
of that layer. The total pullback may be the result of the
high-temperature processing required to manufacture
the package or to coat the surface. It may also be the
result of design considerations (see Figure 3).
5.17 rundown — On a semiconductor package, the
linear distance from the upper surface of a ceramic
cavity layer to the bottom point of the overhang into the
cavity, of a sealing glass or metallization layer that has
been screened onto that surface (see Figure 3).
5.18 seal area — On a semiconductor package, the
area designated for sealing a cover or lid to a cofired
ceramic package, to a cap to a cer-pack base.
SEMI G1-96 © SEMI 1980, 19963
5.19 void — An absence of metallization or glass from
a designated metallized or glassed area on a ceramic
surface.
6 Ordering Information
Purchase orders for cerdip components or sub-
assemblies furnished to this specification shall include
the following items:
6.1 Current drawing revision detai ling:
6.1.1 All dimensions and tolerances per ANSI
Y14.5M practices
6.1.2 Type and color of ceramic
6.1.3 Type and thickness of glass
6.1.4 Type and thickness of die pad metallization
NOTE 3: If sub-assemblies are purchased, the leadframe
details shall be as described in SEMI G2. In some cases,
unlike the frames described in SEMI G2, the leadframes may
also have a die-attach pad. If required, the external lead
plating requirements for these sub-assemblies shall also be
specified. (See SEMI G20 for general details of lead finishes.)
If sub-assemblies are purchased, leadframe inspection shall
follow the requirements detailed in Section 9.
6.2 Incoming Inspection and Functional Tests — See
Sections 9 and 10.
6.3 Incoming Sampling Procedures — See Section 11.
6.4 Packaging and Marking Requirements — See
Section 12.
6.5 Vendor Certification Requirements — See Section
13.
6.6 Any additions to, or variations from, this
specification.
7 Dimensions
The components or sub-assemblies described in this
specification shall produce packaged devices that
conform to the outline dimensions and lead numbering
for cerdip package constructions detailed in:
— JEDEC Publication 95 and
— MIL-STD-1835.
Package manufacturing tolerances shall be agreed upon
between user and supplier and detailed in the drawings.
Typical dimensions and tolerances for standard bases
and caps are shown in the appendices at the end of this
specification.
8 Materials
The definitions defect criteria and functional tests
described in this specification relate to package
components made with the following materials:
8.1 Bases, Window Frames, and Caps
8.1.1 Material — Ceramic with 90% alumina,
minimum content.
8.1.2 Color — Black, dark brown, or dark violet.
8.2 Sealing Material
8.2.1 Material — Solder glass desig ned to seal metal
(typically Iron-Nickel-Cobalt alloy per MIL-M-38150,
Type A or Iron-Nickel alloy per MIL-M-38150 Type B)
to ceramic.
8.3 Die-Attach Pad
8.3.1 Material — Thick film gold or other specified
material.
8.4 Leadframe
8.4.1 Leadframes, whether purchased as component or
in sub-assemblies, shall conform to the requirements of
SEMI G2 as required.
9 Defect Limits
The following defects shall be cause for rejection if the
limits shown are exceeded:
NOTE 4: The criteria apply to purchased components and
pre-assemblies, as applicable, or, where applicable, to units
assembled by the user to process conditions agreed upon
between the user and supplier.
9.1 Ceramic Components
9.1.1 Cracks — Any crack.
9.1.2 Chips — See Figures 1 and 2.
9.1.2.1 Corner Chips — 0.030" (0.762 mm) × 0.030"
(0.726mm) × 25% of the package element thickness.
9.1.2.2 Edge Chips — 0.100" (2.54 mm) × 0.030"
(0.726mm) × 25% of the package element thickness.
9.1.2.3 Critical Seal Area — Chips shall not reduce
the critical seal path, at any point, more than 30%. No
more than four chips are allowed in this area, regardless
of loss of seal length.
9.1.3 Burrs, Projection (Fins), and Blisters
9.1.3.1 Bases, Caps, and Window Frames — 0.005"
(0.127 mm) maximum allowable dimension in the plane
of the component, or greater than 0.003" (0.076 mm) in
height.