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SEMI M51-0303 © SEMI 2002, 2003 6 7 Interferences 7.1 Since this is a DC measurement, care m ust be taken to make sure that the silicon wafer has a low resistance ohmic contact . There m ust be no dielectric film on the …

SEMI M51-0303 © SEMI 2002, 2003 5

some of the proper C-mode events in which the gate

oxide was not broken down are counted B-mode

failures. Both cases will be taken as a mistake in the

classification of the failure modes, even if the

measurement is accurately done and the appropriate I-V

curves measurements are achieved. A dielectric

breakdown judgment current of 10

–5

A is

recommended.

6 Significance and Use

6.1 This standard gives instructions of the procedure

for characterizing mirror-polished, p-type CZ silicon

wafers by measuring the dielectric breakdown defect

density in the thermally grown gate oxide film using the

MOS capacitors. The MOS capacitors must be formed

in accordance with the fabrication process described in

Section 5 that influences the oxide characteristics.

6.2 It is well known that both the silicon surface

morphology and the cross-sectional structure at the

pattern edge of the active region of the MOS devices

influences the dielectric breakdown of the gate oxide.

Various kinds of contaminations also influence the

dielectric breakdown of the gate oxide. Contamination

by alkaline or heavy metals and organic particles

increases as the sample fabrication process progresses.

Furthermore, COPs increase with increasing SC-1

treatment. These facts indicate that it is desirable to

simplify the sample structure and its fabrication

processes to characterize a silicon wafer by TZDB of

the gate oxide. Thermal processes can cause growth of

oxygen precipitates in a silicon wafer. This standard

cannot be applied to silicon wafers that might receive

such thermal processes.

6.3 The appropriate area and the appropriate total

number of the tested MOS capacitors shall be chosen so

as to answer the purpose of this standard test. For

example, as shown in Table R1-3, it is suitable to select

a gate electrode area of 10 mm

and a total number of

capacitors of more than 100.

6.4 The electrode material of the MOS capacitors has a

great influence on the dielectric breakdown of the gate

oxide. Polysilicon is specified as the electrode material

in this standard. It is applied to practical ultra large-

scale integrated circuits (ULSI). The polysilicon

electrode yields test results highly consistent with the

actual ULSI performance.

1E-11

1E-9

1E-7

1E-5

1E-3

1E-1

0 4 8 12 16

Ebd (MV/cm)

Current (A)

Ig > 1E-7 A

-4

-3

-2

-1

0481216

Ebd (MV/cm)

(ln(-ln(1-P)))

B-mode C-mode

-mode

Ig > 1E-3 A Ig > 1E-5 A Ig > 1E-7 A

1E-11

1E-9

1E-7

1E-5

1E-3

1E-1

0 4 8 12 16

Ebd (MV/cm)

Current (A)

Ig > 1E-5 A

-4

-3

-2

-1

0481216

Ebd (MV/cm)

(ln(-ln(1-P)))

B-mode C-mode

-mode

1E-11

1E-9

1E-7

1E-5

1E-3

1E-1

0 4 8 12 16

Ebd (MV/cm)

Current (A)

Ig > 1E-3

-4

-3

-2

-1

0481216

Ebd (MV/cm)

(ln(-ln(1-P)))

B-mode C-modeA-mode

Figure 1

Comparison of Judgment Conditions

SEMI M51-0303 © SEMI 2002, 2003 6

7 Interferences

7.1 Since this is a DC measurement, care must be taken

to make sure that the silicon wafer has a low resistance

ohmic contact. There must be no dielectric film on the

back surface, e.g. silicon oxide, in order to effectively

apply a voltage bias to the gate oxide. It is not

necessary for this to be done with a metallic contact to

the back surface of the wafer under test.

7.1.1 However, when the vacuum chucking is weak,

care must be taken because of the possibility that the

dielectric breakdown voltage of the gate oxide is not

accurately measured due to an increase in parasitic

resistance.

7.2 It is strongly suggested that testing be done with a

voltage polarity such that the silicon surface will be in

accumulation below the gate oxide, that is, negative

voltages for p-type silicon wafers. If the polarity of the

voltage is chosen to be in the reverse direction, the

breakdown voltage may not be accurately measured due

to the presence of a depletion layer below the gate

oxide.

7.3 Evaluation and control of electrical noise in the

current-voltage data, as part of this test method are

crucial to the proper identification of the failure criteria.

7.4 In the TZDB measurement, lowering of the

electrical noise under a low bias stress condition is

made possible by the averaging of measurement data.

While the required 100 ms holding time may be set

using a delay in the measurement loop, an additional,

uncontrolled delay may be incurred due to the

autoranging of an electrometer. The effect is most

pronounced for very low oxide leakage currents, where

the measured value is several orders of magnitude

below the minimum range set by the electrometer

software.

7.5 Mechanical stress by the exploring probe can

influence the measurement results, because the

exploring probe is in contact with the gate electrode

directly on the gate oxide.

7.6 The actual results obtained depend somewhat on

the sample fabrication process. Care must be taken to

ensure consistent processing.

7.7 Wafer temperature during testing shall be clearly

defined. Large temperature variations might have an

impact on results.

7.8 Precaution — Since the voltages and currents

involved are potentially dangerous, appropriate means

of preventing the operator from coming into contact

with the exploring probe or other charge surfaces shall

be in place before testing.

7.9 This standard does not include any clauses relating

to the safety and sanitation of the environment. Those

who intend to implement this standard shall consider

appropriate means to prevent any accidents or disasters,

as well as taking responsibility for maintaining a state

of safety, health and hygiene for users.

8 Apparatus

8.1 The MOS capacitors shall be fabricated in an

environment of 1000 class or better in total quality to

prevent various contaminations. Contamination control

in the processes from the wafer cleaning step to the

polysilicon deposition step is especially important.

Contamination during those processes has been

reported to degrade GOI. Therefore, attention must be

paid to those processes in particular.

8.2 High purity deionized water and high purity

chemicals of electronics industry grade shall be used in

the processes of wafer cleaning, wet etching, etc. The

chemical/pure water grade and guide are referenced in

SEMI Standards C21, C27, C28, C30, C35, C38, C41,

and C44; and ASTM D5127.

8.3 In thermal processes such as gate oxidation,

polysilicon deposition, and phosphorus doping,

fluctuations in process temperature may affect the

uniformity of oxide thickness, polysilicon thickness,

and the concentration and distribution of doped

phosphorus atoms. The temperature fluctuation of used

furnaces shall be within ± 5°C at the most.

8.4 Quartz is very resistant to the strong acids––

excluding hydrofluoric acid––and alkalis used in wet

processes and at temperatures higher than 1000°C.

Therefore, quartz vessels, tubes, and so on are quite

frequently used in the ULSI manufacturing processes.

High-purity quartz vessels and tubes of electronics

industry grade shall also be used in this MOS capacitor

fabrication process.

8.5 High-purity gases of electronics industry grade,

such as N

, O

and SiH

, shall be used in the processes

of thermal oxidation, polysilicon deposition,

phosphorous doping, and so on to prevent

contamination from the gases. The process gas grade

and guide are referred in SEMI Standards C3.6, C3.21,

C3.22, C3.23, C3.28, C3.41, C3.49, and C3.54.

8.6 A criterion for evaluating a clean room

environment where MOS samples are fabricated for this

test method is that the A-mode failure percent of the

samples with 20–25 nm oxide is less than 10%. It is

advisable that the level of cleanliness of the clean room

environment where the tested MOS capacitors are

fabricated is evaluated by TZDB measurement of the

MOS capacitors on an epitaxial wafer.

SEMI M51-0303 © SEMI 2002, 2003 7

8.7 ASTM standard F1771 shall be applied for

measurement equipment such as voltage source units

and manual probing machines.

9 Sampling

9.1 Sampling is the responsibility of the user of this

test method. However, if testing is done as part of

comparison or correlation, all participants shall agree

upon sampling in advance.

NOTE 9: Refer to the appendix of JEDEC 35 for a good

discussion of sampling plan statistics.

10 Procedure

10.1 Fabrication of MOS Capacitors

10.1.1 It shall be confirmed first that the environment

for fabricating MOS capacitors is suitable for this test

method. The environment includes clean room,

chemicals, ultra pure deionized water, oxidation

furnace, polysilicon deposition equipment, different

kinds of quartz jigs, etc. As a criterion for evaluating

the suitability of an environment, the A-mode failure

percent of the MOS capacitors made in the environment

shall be less than 10%.

10.1.2 To characterize proper silicon wafers, the

wafers shall not be cleaned. If the wafers might

contaminate a furnace, they shall be cleaned before

oxidation. In these cases, the wafers are cleaned by a

modified RCA method, in general.

10.1.3 Input oxidation parameters in the used furnace

system. The parameters include oxidation temperature,

ambient, gas flow rate, oxidation time, etc. A

recommended oxidation temperature is 850–950°C.

The appropriate parameters for obtaining the

recommended oxide thickness (20−25 nm) shall be

found out in advance by preliminary testing.

10.1.4 Oxidize the wafers into dry oxygen ambient.

Some reference wafers shall be treated together with the

sample wafers to monitor the oxide thickness and sheet

resistance of polysilicon electrodes. The number of

reference wafers shall be decided on by the users of this

test method, taking into account of the quantity of the

total wafers in the batch.

10.1.5 Measure the oxide thickness of the reference

wafers by ellipsometry (or another optical method) to

confirm the uniformity of the oxide thickness within the

wafers. The average thickness shall be in the range 20–

25 nm and the dispersion within a wafer shall be less

than ± 3%.

10.1.6 Input deposition parameters of polysilicon into a

used LP-CVD furnace system. The parameters include

deposition temperature, pressure, gas flow rate,

deposition time, etc. The appropriate conditions for

obtaining the recommended polysilicon thickness (200–

400 nm) shall be found out in advance by preliminary

testing. If a doped polysilicon film will be deposited,

corresponding deposition parameters shall be input.

10.1.7 Deposit a polysilicon film on the wafers

oxidized. The recommended deposition temperature

for this test method is 570–640°C. Some reference

wafers with an oxide shall be treated together with the

sample wafers to monitor the polysilicon thickness.

The oxide thickness on the reference wafers shall be

recommended by a vendor of equipment to measure the

thickness of the polysilicon films. The number of

reference wafers shall be decided on by the users of this

test method taking into account the total quantity of

wafers in the batch.

10.1.8 Measure the polysilicon thickness on the

reference wafers using a spectroscopic reflectometer (or

other optical film thickness measurement instruments)

to confirm the uniformity of the polysilicon film

thickness within a wafer and within a batch. The

average polysilicon film thickness shall be 200–400 nm

and dispersion within a batch shall be less than ± 10%.

If doped polysilicon was deposited, proceed to Section

10.1.11.

10.1.9 Input the doping parameters to a phosphorus-

doping furnace system. The parameters include doping

temperature, ambient, phosphorous source, carrier gas

flow rate, doping time, etc. POCl

is a well-known

phosphorous source. Those process parameters will

affect polysilicon resistance and uniformity. The

appropriate process parameters for obtaining the

recommended sheet resistance (20−50 Ω/sq) shall be

found out in advance by preliminary testing.

10.1.10 Dope phosphorus into the polysilicon film on

the silicon wafers. The reference wafers shall be doped

together with the sample wafers to check the

polysilicon film resistance.

10.1.11 Measure the sheet resistance of the reference

wafers using a resistance meter to confirm the

uniformity of resistance within a wafer and within a

batch. The average resistance shall be 20–50 Ω/sq and

the dispersion within the batch shall be less than ± 10%.

10.1.12 Make a resist mask pattern using

photolithography techniques. The recommendation for

the gate electrode pattern of the MOS capacitors in this

test method is to form more than 100 capacitors with a

gate electrode area of 10 mm

within a wafer.

10.1.13 Etch the polysilicon film to form MOS

capacitors. At the same time, the backside polysilicon

film shall be etched. If a dry etching method is used,