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SEMI M17-0704 © SEMI 1990, 2004 1 SEMI M17-0704 GUIDE FOR A UNIVERSAL WAFER GRID This specification was technically approved by th e Global Silicon Wafer Committee and is the direct responsibility of the North American S…

SEMI M16-1103 © SEMI 1989, 2003 5

R1-3.1.2 SEMI M16 specifies that samples for

photoluminescence and infrared measurements are to be

prepared from nugget and rod forms in accordance with

SEMI MF1723 and from granular form in accordance

with SEMI MF1708. Samples for atomic absorption

spectroscopy measurements are to be prepared in

accordance with SEMI MF1724.

R1-3.1.3 The preparation procedures are generally

similar, except that JIS H 0615 allows coring only

perpendicular to the rod filament, but SEMI MF1723

permits coring parallel with the rod filament in addition

to perpendicular to the rod filament.

R1-3.2 Measurement Procedures

R1-3.2.1 The photoluminescence technique is specified

for measurement of donor and acceptor concentrations

in both JEITA EM-3601 and in SEMI M16 (through

reference to SEMI MF1723); the latter also allows this

determination by low temperature FT-IR analysis. The

photoluminescence technique is covered in SEMI

MF1389 and in JIS H 0615. The latter, specified in

JEITA EM-3601, allows only the high excitation

condition for the photoluminescence analysis while the

former allows either high or low excitation.

R1-3.2.2 The infrared absorption method is specified

for the carbon determination in both SEMI M16 and

JEITA EM-3601. The two cited test methods, SEMI

MF1391, specified in SEMI M16 (through reference to

SEMI MF1723), and JEITA EM-3503, cited in JEITA

EM-3601, are essentially equivalent.

R1-3.2.3 Atomic absorption spectroscopy is specified

for the surface metal contamination in both SEMI M16

and JEITA EM-3601. The two cited test methods,

SEMI MF1724, specified in SEMI M16, and JIS K

0121, cited in JEITA EM-3601, are essentially

equivalent insofar as the actual measurement is

concerned, but SEMI MF1724 also standardizes the

sampling procedures, etching solutions, and method of

collecting the impurities in much greater detail.

NOTICE: SEMI makes no warranties or

representations as to the suitability of the standards set

forth herein for any particular application. The

determination of the suitability of the standard is solely

the responsibility of the user. Users are cautioned to

refer to manufacturer’s instructions, product labels,

product data sheets, and other relevant literature

respecting any materials mentioned herein. These

standards are subject to change without notice.

The user’s attention is called to the possibility that

compliance with this standard may require use of

copyrighted material or of an invention covered by

patent rights. By publication of this standard, SEMI

takes no position respecting the validity of any patent

rights or copyrights asserted in connection with any

item mentioned in this standard. Users of this standard

are expressly advised that determination of any such

patent rights or copyrights, and the risk of infringement

of such rights, are entirely their own responsibility.

International), 3081 Zanker Road, San Jose, CA 95134. Reproduction o

the contents in whole or in part is forbidden without express written

consent of SEMI.

SEMI M17-0704 © SEMI 1990, 2004 1

SEMI M17-0704

GUIDE FOR A UNIVERSAL WAFER GRID

This specification was technically approved by the Global Silicon Wafer Committee and is the direct

responsibility of the North American Silicon Wafer Committee. Current edition approved by the North

American Regional Standards Committee on April 22, 2004. Initially available at www.semi.org May 2004;

to be published July 2004. Originally published in 1990; previously published September 1998.

1 Purpose

1.1 Maximum allowable slip and other non-uniformly

distributed defects are frequently specified when

procuring polished and epitaxial silicon wafers. SEMI

M2 specifies a maximum allowable fraction of the

epitaxial wafer surface area that can contain slip.

1.2 This guide provides a design for and guidance for

use of a wafer grid that facilitates the determination of

the fraction of the wafer surface area covered by

observed defects.

2 Scope

2.1 This document defines a grid pattern that is useful

for quantifying surface defects on a nominally circular

semiconductor wafer. The grid is defined such that it

contains 1000 elements of approximately equal area.

Each grid element thus contains 0.1 percent of the total

quality area of the surface being inspected. Defects that

are non-uniformly distributed (for example, slip) can be

quantified in terms of the percent defective (or percent

useful) area on the wafer surface.

2.2 The grid described is referenced to the center of the

wafer. A concept of a “Fixed Quality Area” is used,

based on nominal wafer diameter, such as is specified

in SEMI M1.

2.3 Methods for observing these defects on silicon

wafer surfaces are outside the scope of this guide. Such

methods may be found in SEMI MF1725, SEMI

MF1726, JIS H 0609, and DIN 50434.

NOTICE: This standard does not purport to address

safety issues, if any, associated with its use. It is the

responsibility of the users of this standard to establish

appropriate safety and health practices and determine

the applicability of regulatory or other limitations prior

to use.

3 Referenced Standards

3.1 SEMI Standards

SEMI M1 — Specifications for Polished

Monocrystalline Silicon Wafers

SEMI M2 — Specifications for Silicon Epitaxial

Wafers for Discrete Device Applications

SEMI MF154 —Guide for Identification of Structures

and Contaminants Seen on Specular Silicon Surfaces

SEMI MF1241 — Terminology of Silicon Technology

SEMI MF1725 — Practice for Analysis of

Crystallographic Perfection of Silicon Ingots

SEMI MF1726 — Practice for Analysis of

Crystallographic Perfection of Silicon Wafers

SEMI MF1809 — Guide for Selection and Use of

Etching Solutions to Delineate Structural Defects in

Silicon

3.2 Japan Industrial Standard

JIS H 0609 — Test methods of crystalline defects in

silicon by preferential etch techniques

3.3 DIN Standard

50434 — Determination of Crystal Defects in

Monocrystalline Silicon Using Etching Techniques on

{ 111} and { 100} Surfaces

NOTICE: Unless otherwise indicated, all documents

cited shall be the latest published versions.

4 Terminology

4.1 Definitions for many surface defects are given in

SEMI MF1241. Additional information and illustrations

of various surface defects are provided in SEMI

MF154, SEMI MF1809, and JIS H 0609.

5 Grid Element Layout

5.1 Grid Element Scheme

5.1.1 Two types of grids are defined: one for wafers

without a primary flat (for example, wafers where the

primary fiducial is a notch), and one for wafers with a

primary flat. The grid is divided by 18 concentric

circles containing radial divisions which are assigned

according to the diameter of each circle (see Table 1).

The relative diameters of the concentric circles are

established by the areas of each annulus. To find the

1 Available, in Japanese language edition only, through the Japanese

Standards Association, 1-24, Akasaka 4-Chome, Minato-ku, Tokyo

107-8440, Japan. Telephone: 81.3.3583.8005; Fax: 81.3.3586.2014

Website: www.jsa.or.jp

2 Available from Deutches Institut für Normung e.V., Beuth Verlag

GmbH, Burggrafenstrasse 4-10, D-10787 Berlin, Germany, website:

www.din.de

SEMI M17-0704 © SEMI 1990, 2004 2

actual diameter of any circle, multiply the relative

diameter by the outer diameter of the grid.

5.1.2 The outer diameter of the grid is chosen to be the

size appropriate for a particular application. This

diameter would normally be chosen to be the nominal

diameter of the fixed quality area to allow for such

things as an edge exclusion, tolerance variations in the

wafer diameter, and edge rounding. Table 2 shows the

circle diameters for a series of grids which have a fixed

quality area radius 3 or 4 mm smaller than the nominal

radius of selected wafers specified in SEMI M1.

5.1.3 Identification of each grid element is done by

referring to a circle number and a division number on

that circle. Circles are numbered from the center out,

with the center circle being number 01 and the

outermost circle being number 18. The divisions are

numbered starting with the first division

counterclockwise from the horizontal line which starts

at the center of the grid and extends to the right, when

the primary fiducial (flat or notch) is placed at the

bottom of the grid. Divisions are progressively

numbered counterclockwise from 01 to n, where n

equals the total number of divisions on the circle. An

element’s address is given by two sets of numbers

separated by a comma: circle (0–18), division (01–n).

Elements 18, 01 and 18, 100 are identified in Figure 1.

5.2 Wafers without a Primary Flat

5.2.1 The grid elements for wafers without a primary

flat are illustrated in Figure 1. This pattern is generated

by making concentric circles with relative diameters

and radial divisions as specified in Table 1. In this table

the circle number is given in the leftmost column. The

number of divisions and the included angle of each

division in the circle are given in the second and third

columns. The total number of divisions (from the center

outward) is given in the fourth column. The included

area ratio, given in the fifth column, is the total number

of divisions included within a circle divided by 1000,

the total number of divisions in the grid. The relative

diameter, given in the rightmost column, is the square

root of the included area ratio.

5.3 Wafers with a Primary Flat

5.3.1 For wafers with a primary flat, a standard

included angle of 43.2° is used for all wafer sizes. This

angle was chosen because it lies between the maximum

and minimum included angles of the primary flats

specified in SEMI M1 for 100 mm, 125 mm, 150 mm,

and 200 mm diameter wafers. In addition, if a fixed

quality area of radius 3 mm less than the nominal wafer

radius (or smaller) is used, the grid will not in any case

extend beyond the edge of the wafer in the region of the

primary flat.

5.3.2 This flat is propagated into the wafer as

illustrated in Figure 2. The diameter of each circle is the

same as for wafers without a primary flat. The flat is

propagated vertically downward (starting with circle

number 3) by the intersection of the circle with a

horizontal chord which subtends 43.2° .

5.3.3 The areas of the grid elements within the

propagated flat region are slightly smaller than the areas

of the regular grid elements. This difference is ignored

when counting grid elements for wafers with a primary

flat. All grid elements are assumed to be 0.001 of the

total fixed quality area.

5.4 Secondary Flats

5.4.1 The grid ignores secondary flats. These are

shallow enough that the outer circle does not extend

beyond the wafer edge if a fixed quality area of radius 3

mm less than the nominal wafer radius is used.

NOTE 1: In this sense, the fixed quality area used by the

Universal Wafer Grid deviates somewhat from the formal

definition in SEMI M1 which embodies an edge exclusion of

constant width around the entire periphery of the wafer

including the region of the secondary flat.

6 Use of the Grid

6.1 The quantification of defective area is done by

overlaying a transparency of the grid onto a map of

wafer defects or by mapping observed defects onto the

grid. The number of grid elements which contain

defects is counted. The element count divided by 10

corresponds to the percent of defective area. This grid

could also be superimposed onto a CRT display,

photograph, or computer generated map, where

applicable. In use, grid pattern diameters must be

scaled to the size of the map or image of the wafer to be

overlaid.