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SEMI M1-0305 © SEMI 1978, 2005 3 1 Purpose 1.1 Monocrystalline (sing le crystal) silic on wafers are utilized for essentially all in tegrated circuits and many other semiconductor devices. To permit common processing equ…

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SEMI M1-0305 © SEMI 1978, 2005 2
R2-4 Electrical Characteristics ..............................................................................................................................45
R2-5 Chemical Characteristics ..............................................................................................................................46
R2-6 Structural Characteristics..............................................................................................................................46
R2-7 Dimensional Characteristics .........................................................................................................................46
R2-8 Front Surface Chemistry ...............................................................................................................................48
R2-9 Surface Inspection Characteristics ................................................................................................................48
List of Tables
Table 1 Silicon Wafer Specification Format for Order Entry, Parts 1 and 2 ..............................................................10
Table 2 Energy Ranges for Ion Implant Modeling .....................................................................................................20
Table 3 Wafer Edge Profile Template Coordinates....................................................................................................24
Table 4 Dimensional Characteristics of 2 in. and 3 in. Polished Monocrystalline Silicon Wafers.............................25
Table 5 Dimensional Characteristics of 100 mm and 125 mm Polished Monocrystalline Silicon Wafers with
Secondary Flat......................................................................................................................................................26
Table 6 Dimensional Characteristics of 150 mm Polished Monocrystalline Silicon Wafers with Secondary
Flat........................................................................................................................................................................27
Table 7 Dimensional Characteristics of 100 mm and 125 mm Polished Monocrystalline Silicon Wafers without
Secondary Flat......................................................................................................................................................28
Table 8 Dimensional Characteristics of 150 mm and 200 mm Polished Monocrystalline Silicon Wafers without
Secondary Flat......................................................................................................................................................29
Table 9 Dimensional Characteristics and Wafer ID Marking Requirements for Notched 200 mm and 300 mm
Polished Monocrystalline Silicon Wafers ............................................................................................................30
Table 10 Polished Wafer Defect Limits .....................................................................................................................32
Table 11 Basic Specification for 300 mm Polished Prime Silicon Wafers for the 130-nm Technology Node ..........33
Table A2-1 Variables in Shape Quantities..................................................................................................................42
Table A2-2 Shape Code Summary .............................................................................................................................42
Table R1-1 Suggested Polished Wafer Surface Metal Contamination Limits Appropriate to Circuits and Devices
with a Minimum Linewidth in the Range 0.8 µm to 1.2 µm................................................................................43
List of Figures
Figure 1 Fixed Quality Area.......................................................................................................................................18
Figure 2 Orthogonal Misorientation of {111} Wafer .................................................................................................19
Figure 3 Optional A/N Code Field Location on Back Surface of Notched 300 mm Diameter Wafer
(Category 1.15) ....................................................................................................................................................21
Figure 4 Secondary Flat Locations .............................................................................................................................22
Figure 5 Notch Dimensions........................................................................................................................................23
Figure 6 SEMI Edge Profile Template .......................................................................................................................23
Figure 7 Examples of Acceptable and Unacceptable Wafer Edge Profiles ................................................................24
Figure A1-1 Flatness Decision Tree ...........................................................................................................................38
Figure A1-2 Scanner Site and Subsite Flatness Elements ..........................................................................................39
Figure A1-3 Subsite Center near Boundaries of Site and FQA ..................................................................................39
Figure A2-1 Four Branches of the Shape Decision Tree............................................................................................41
SEMI M1-0305 © SEMI 1978, 2005 3
1 Purpose
1.1 Monocrystalline (single crystal) silicon wafers are utilized for essentially all integrated circuits and many other
semiconductor devices. To permit common processing equipment to be used in multiple device fabrication lines, it
is essential for the wafer dimensions to be standardized.
1.2 In addition, as technology advances to smaller and smaller dimensions for the elements of high density
integrated circuits, it has become of interest to standardize additional properties of the wafers.
1.3 This specification provides the essential dimensional and certain other common characteristics of silicon wafers,
including polished wafers as well as substrates for epitaxial and certain other kinds of silicon wafers.
2 Scope
2.1 These specifications cover ordering information and certain requirements for high-purity, monocrystalline
polished silicon wafers used in semiconductor device and integrated circuit manufacturing or as substrates (or
starting wafers) for other kinds of wafers, including epitaxial, annealed, and SOI wafers.
2.2 Dimensional requirements are provided for the following categories of polished wafers:
Category 1.1 2 in. polished monocrystalline silicon wafers with secondary flat
Category 1.2 3 in. polished monocrystalline silicon wafers with secondary flat
Category 1.5 100 mm polished monocrystalline silicon wafers, 525 m thick, with secondary flat
Category 1.6 100 mm polished monocrystalline silicon wafers, 625 m thick, with secondary flat
Category 1.7 125 mm polished monocrystalline silicon wafers with secondary flat
Category 1.8.1 150 mm polished monocrystalline silicon wafers with secondary flat and T/3 edge profile
template
Category 1.8.2 150 mm polished monocrystalline silicon wafers with secondary flat and T/4 edge profile
template
Category 1.9.1 200 mm notched polished monocrystalline silicon wafers with T/3 edge profile template
Category 1.9.2 200 mm notched polished monocrystalline silicon wafers with T/4 edge profile template
Category 1.10.1 200 mm flatted polished monocrystalline silicon wafers with T/3 edge profile template
without secondary flat
Category 1.10.2 200 mm flatted polished monocrystalline silicon wafers with T/4 edge profile template
without secondary flat
Category 1.11 100 mm flatted polished monocrystalline silicon wafers without secondary flat
Category 1.12 125 mm flatted polished monocrystalline silicon wafers without secondary flat
Category 1.13.1 150 mm flatted polished monocrystalline silicon wafers with T/3 edge profile template
without secondary flat
Category 1.13.2 150 mm flatted polished monocrystalline silicon wafers with T/4 edge profile template
without secondary flat
Category 1.15 300 mm notched polished monocrystalline silicon wafers
2.2.1 Values given for thickness, TTV, bow, and warp apply only to wafers prior to application of back surface
films, extrinsic gettering treatments, or other thermal treatments.
2.2.2 The dimensional characteristics of Category 1.10.1, 1.10.2, 1.11, 1.12, 1.13.1, and 1.13.2 wafers specified in
this document are identical with those specified in JEITA EM-3602, and the dimensional characteristics of Category
1.15 wafers are essentially equivalent with those specified in JEITA EM-3602.
SEMI M1-0305 © SEMI 1978, 2005 4
2.3 A complete purchase specification requires that additional physical properties be specified along with test
methods suitable for determining their magnitude. This standard provides a comprehensive listing of such
properties and associated test methods. This listing provides a systematic basis for constructing the purchase
specification for any kind of polished silicon wafer or substrate and is expected to be used for such purposes.
2.4 These specifications apply specifically to prime silicon wafers with at least one chem-mechanically polished
surface. Ground, lapped, and unpolished wafers are not covered in this specification but this specification may
provide guidance in connection with their procurement.
2.5 In addition, these specifications cover specification requirements for basic 300 mm diameter, double-side
polished silicon wafers that are suitable for many advanced integrated circuit applications. If this kind of wafer is
desired, physical properties other than those listed in the table of requirements shall not be included in the purchase
specification.
2.6 These specifications do not cover the requirements for the following related silicon materials and wafers:
Polycrystalline silicon (see SEMI M16 or JEITA EM-3601),
Epitaxial wafers (see SEMI M2 or SEMI M11),
Epitaxial wafers with buried layer (see SEMI M18),
Test wafers (see SEMI M8),
Premium wafers (see SEMI M24),
Reclaimed wafers (see SEMI M38),
Annealed wafers (see SEMI M57),
SOI wafers (see SEMI M34, SEMI M41, SEMI M47, or JEITA EM-3603),
Dielectrically isolated wafers (see SEMI M22), and
Solar-grade silicon wafers (see SEMI M6).
They do, however, provide the ordering information for test, premium, and reclaimed wafers, as well as the ordering
information for the polished substrates and starting wafers used to prepare epitaxial, annealed, and SOI wafers.
2.7 The complete EDI Code List for items in the Order Form appropriate to silicon wafers, including polished
wafers and substrates, can be found in SEMI M18.
2.8 For referee purposes, U.S. customary units shall be used for wafers of 2 in. and 3 in. nominal diameters, and SI
(system international, commonly called metric) units for 100 mm and larger diameter wafers.
NOTICE: This standard does not purport to address safety issues, if any, associated with its use. It is the
responsibility of the user of this standard to establish appropriate safety and health practices and determine the
applicability of regulatory or other limitations prior to use.
3 Referenced Standards
3.1 SEMI Standards
SEMI M2 — Specification for Silicon Epitaxial Wafers for Discrete Device Applications
SEMI M6 — Specification for Silicon Wafers for Use as Photovoltaic Solar Cells
SEMI M8 — Specification for Polished Monocrystalline Silicon Test Wafers
SEMI M11 — Specifications for Silicon Epitaxial Wafers for Integrated Circuit (IC) Applications
SEMI M12 — Specification for Serial Alphanumeric Marking of the Front Surface of Wafers
SEMI M13 — Specifications for Alphanumeric Marking of Silicon Wafers
SEMI M16 — Specification for Polycrystalline Silicon
SEMI M18 — Format for Silicon Wafer Specification Form for Order Entry