semi合集-English.pdf - 第6491页

SEMI G79-0200 © SE MI 2000 4 7.1.2.4 Output Timing Jitter — short te r m ( cycle to cycle) instability using any pin, any co mpare timing edge, win dow or strobe com pare mode, expect H or L . Condition s: • error expres…

100%1 / 7923
SEMI G79-0200 © SEMI 20003
6.2.4 Examination of the OTA definition in the con-
text of Figure 1, that being the general case and not a
single point timing evaluation, reveals that the overall
timing accuracy time value is the time line indicated by
“A” and the time line indicated by “B”. In a single
point AC timing evaluation, OTA is determined as a
distribution of edges associated with time line “A” or
time line “B”, depending upon the relationship between
the drive edge values and compare edge values (see
Section 7.1.3) at that point in time.
7 Definitions
7.1 Overall Timing Accuracy — aggregate timing
error comprised of input edge placement accuracy,
output edge placement accuracy and input to output
timing accuracy. (See Figure 1.)
7.1.1 Input Edge Placement Accuracy — DUT input
timing error comprised of input timing delay error,
input timing jitter and input transition time variation.
7.1.1.1 Input Timing Delay Error @ 5V — time delay
error at the midpoint of a 5V transition, with respect to
an ideal delay (NIST traceable delay reference), using
any pin, any delay value, any input timing edge, any
format (NR, Rtx, SBx), positive or negative transition
and any test cycle length.
Conditions:
• delays are normalized to pin 1 (first tester pin),
rising edge, NR format, @ 0ns;
• errors are normalized to the average of minimum
and maximum of the error distribution;
1
• reference load A; and
• physical reference point is a zero length
interconnect on the DUT side of a standard
performance board.
7.1.1.2 Input Timing Delay Error @ 3V — (same as
Section 7.1.1.1 @ 3V)
7.1.1.3 Input Timing Delay Error @ 1V — (same as
Section 7.1.1.1 @ 1V)
7.1.1.4 Input Timing Jitter — short term (cycle to
cycle) instability using any pin, any input timing edge,
any format (NR, RTx, SBx).
Conditions:
• error expressed as RMS value;
• reference load B;
1 “Average of min and max of the error distribution” is defined as:
(min error + max error)/2. This can also be referred to as “center
of spread”.
• physical reference point is a zero length intercon-
nect on the DUT side of a standard performance
board; and
• error referenced to corresponding transition of
prior cycle.
7.1.1.5 Input Transition Time Variation @ 5V —
minimum and maximum rise and fall times of a 5V
input signal transition using any pin.
Conditions:
• referenced to the time variation between the 20%
and 80% points of both positive and negative
signal transitions;
• reference load A; and
• physical reference point is a zero length intercon-
nect on the DUT side of a standard performance
board.
7.1.1.6 Input Transition Time Variation @ 3V —
(same as Section 7.1.1.5 @ 3V)
7.1.1.7 Input Transition Time Variation @ 1V —
(same as Section 7.1.1.5 @ 1V)
7.1.2 Output Edge Placement Accuracy — DUT
output compare timing error comprised of output timing
delay error and output compare timing jitter.
7.1.2.1 Output Timing Delay Error @ 5V — time
delay error at the detected midpoint of a 5V transition,
with respect to an ideal delay (NIST traceable refer-
ence), using any pin, any delay value, any compare
timing edge, window or strobe compare mode, expect H
or L, positive or negative transition and any test cycle
length.
Conditions:
• measured with load circuit “off” or high
impedance;
• delays normalized to rising edge detected by pin 1
(first tester pin), using strobe compare format,
expect H @ 0ns;
• error normalized to the average of minimum and
maximum of the error distribution; and
• input signal: 50-ohm source, 0–5V step, > 1V/ns,
inserted at a zero length interconnect on the DUT
side of a standard performance board.
7.1.2.2 Output Timing Delay Error @ 3V— (same as
Section 7.1.2.1 using 3V input signal)
7.1.2.3 Output Timing Delay Error @ 1V — (same as
Section 7.1.2.1 using 1V input signal)
SEMI G79-0200 © SEMI 2000 4
7.1.2.4 Output Timing Jitter— short term (cycle to
cycle) instability using any pin, any compare timing
edge, window or strobe compare mode, expect H or L.
Conditions:
• error expressed as RMS value;
• physical reference point is a zero length intercon-
nect on the DUT side of a standard performance
board; and
• jitter referenced to an independent synchronous
trigger.
7.1.3 Input to Output Timing Accuracy — relative
time difference between the average of minimum and
maximum drive input delay timing and the average of
minimum and maximum compare output delay timing.
7.1.3.1 Input to Output Timing Error @ 5V — relative
time difference between the average of minimum and
maximum input delay timing error @ 5V (Section
7.1.1.1) and the average of minimum and maximum
output timing delay error @ 5V (Section 7.1.2.1).
Conditions:
• (same as Sections 7.1.1.1 and 7.1.2.1).
7.1.3.2 Input to Output Timing Error @ 3V — same as
Section 7.1.3.1 using 3V input signal and definitions/
conditions specified in Sections 7.1.1.2 and 7.1.2.2.
7.1.3.3 Input to Output Timing Error @ 1V — same as
Section 7.1.3.1 using 1V input signal and definitions/
conditions specified in Sections 7.1.1.3 and 7.1.2.3.
7.1.4 High Speed Clock Accuracy — DUT high speed
clock input timing error (if different than normal tester
input channels) comprised of high speed clock delay
error, high speed clock self-trigger cycle jitter, high
speed clock self-trigger phase jitter and high speed
clock transition time variation.
7.1.4.1 High Speed Clock Delay Error @ 5V — time
delay at the midpoint of a 5V transition, with respect to
an ideal delay (NIST traceable delay reference), using
any pin, any delay value, any input timing edge, RTZ
format, and any test cycle length.
Conditions:
• delays are normalized to pin 1 (first tester pin),
rising edge, NR format, @ 0ns;
• errors are normalized to the average of minimum
and maximum of the error distribution;
• reference load A; and
• physical reference point is a zero length intercon-
nect on the DUT side of a standard performance
board.
7.1.4.2 High Speed Clock Delay Error @ 3V — (same
as Section 7.1.4.1 @ 3V)
7.1.4.3 High Speed Clock Delay Error @ 1V — (same
as 7.1.4.1 @ 1V)
7.1.4.4 High Speed Clock Self-trigger Cycle Jitter —
short term instability using any high speed clock pin,
from a rising clock edge to the next rising clock edge,
or falling clock edge to the next falling clock edge.
Conditions:
• error expressed as RMS value;
• reference load B; and
• physical reference point is a zero length
interconnect on the DUT side of a standard
performance board.
7.1.4.5 High Speed Clock Self-trigger Phase Jitter —
short term instability using any high speed clock pin,
from a rising clock edge to the next falling clock edge,
or falling clock edge to the next rising clock edge.
Conditions:
• error expressed as RMS value;
• reference load B; and
• physical reference point is a zero length
interconnect on the DUT side of a standard
performance board.
7.1.4.6 High Speed Clock Transition Time Variation
@ 5V — minimum and maximum rise and fall times of
a 5V input signal transition using any high speed clock
pin.
Conditions:
• referenced to the 20% and 80% points of a positive
and negative signal transition;
• reference load A; and
• physical reference point is a zero length
interconnect on the DUT side of a standard.
7.1.4.7 High Speed Clock Transition Time Variation
@ 3V — (same as Section 7.1.4.6 @ 3V)
7.1.4.8 High Speed Clock Transition Time Variation
@ 1V — (same as Section 7.1.4.6 @ 1V)
7.1.5 Input Timing Delay Error for Z to Drive
High/Low — Time delay error at the midpoint of a
driver transition from Z to high/low, with respect to an
ideal delay, using any pin, any delay value, any Z
SEMI G79-0200 © SEMI 20005
control timing edge, any Z transition format, and any
test cycle length.
NOTE 3: This definition does not include I/O timing
restrictions imposed by the round trip delay between the tester
electronics and the DUT.
Conditions:
• delays are normalized to pin1 (first tester pin),
rising edge, NR format, 5V, @ 0ns;
• errors are normalized to the average of minimum
and maximum of the error distribution;
• reference load C; and
• physical reference point is a zero length intercon-
nect on the DUT side of a standard performance
board.
7.1.6 Input Timing Delay Error for Drive High/Low to
Z — Time delay error at the midpoint of a driver
transition from high/low to Z, with respect to an ideal
delay, using any pin, any delay value, any Z control
timing edge, any Z transition format, and any test cycle
length.
NOTE 4: This definition does not include I/O timing
restrictions imposed by the round trip delay between the tester
electronics and the DUT.
Conditions:
• delays are normalized to pin1 (first tester pin),
rising edge, NR format, 5V, @ 0ns;
• errors are normalized to the average of minimum
and maximum of the error distribution;
• reference load C; and
• physical reference point is a zero length intercon-
nect on the DUT side of a standard performance
board.
NOTICE: SEMI makes no warranties or represent-
ations as to the suitability of the standard set forth
herein for any particular application. The determination
of the suitability of the standard is solely the
responsibility of the user. Users are cautioned to refer
to manufacturer’s instructions, product labels, product
data sheets, and other relevant literature respecting any
materials mentioned herein. These standards are
subject to change without notice.
The user’s attention is called to the possibility that
compliance with this standard may require use of copy-
righted material or of an invention covered by patent
rights. By publication of this standard, SEMI takes no
position respecting the validity of any patent rights or
copyrights asserted in connection with any item
mentioned in this standard. Users of this standard are
expressly advised that determination of any such patent
rights or copyrights, and the risk of infringement of
such rights, are entirely their own responsibility.
Copyright by SEMI® (Semiconductor Equipment and Materials
International), 3081 Zanker Road, San Jose, CA 95134. Reproduction o
f
the contents in whole or in part is forbidden without express written
consent of SEMI.