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SEMI M24-1103 © SEMI 1994, 2003 4 5.2 Items which m ay be specified when ordering silicon wafers are listed in attached sp ecification tables. Not all of these items are required for ord ering premium wafers . 6 Dimensio…
SEMI M24-1103 © SEMI 1994, 2003 3
50441/1 — Determination of the Geometric
Dimensions of Semiconductor Slices: Measurement of
Thickness
50441/2 — Determination of the Geometric
Dimensions of Semiconductor Slices: Testing of Edge
Rounding
50441/4 — Determination of the Geometrical
Dimensions of Semiconductor Slices: Diameter and
Flat Depth of Slices
50443/1 — Recognition of Defects and Inhomogenities
in Semiconductor Single Crystals by X-Ray
Topography: Silicon
50445 — Contactless Determination of the Electrical
Resistivity of Semiconductor Wafers with the Eddy
Current Method
3.5 JEITA Standards
4
JEIDA 18 — Determining the Orientation of a
Semiconductor Silicon Single Crystal
JEIDA 27 — Standard Specification for Dimensional
Properties of Silicon Wafers with Specular Surface
JEIDA 43 — Terminology of Silicon Wafer Flatness
JEIDA 53 — Test Method for Recombination Lifetime
in Silicon Wafers by Measurement of
Photoconductivity Decay by Microwave Reflectance
JEIDA 56 — Standard Test Method for Substitutional
Atomic Carbon Content of Silicon by Infrared
Absorption
JEIDA 61 — Standard Test Method for Interstitial
Atomic Oxygen Content of Silicon by Infrared
Absorption
3.6 JIS Standards
5
H 0602 — Testing Method of Resistivity for Silicon
Crystals and Silicon Wafers with Four-Point Probe
H 0607 — Testing Methods for Conductivity Type of
Semiconductor Materials
H 0609 — Test Methods of Crystalline Defects in
Silicon by Preferential Etch Techniques
H 0611 — Methods of Measurement of Thickness,
Taper, and Bow of Silicon Wafers
4 Japanese Electronic and Information Technology Industries
Association, Tokyo Chamber of Commerce and Industry Bldg. 2-2,
Marunouchi 3-chome, Chiyoda-ku, Tokyo 100-0005, Japan.,
Website: www.jeita.or.jp
5 Japanese Industrial Standards, Available through the Japanese
Standards Association, 1-24, Akasaka 4-Chome, Minato-ku, Tokyo
107-8440, Japan. Telephone: 81.3.3583.8005; Fax: 81.3.3586.2014,
Website: www.jsa.or.jp
H 0614 — Visual Inspection for Silicon Wafers with
Specular Surfaces
Z8741 — Method of Measurement for Specular
Glossiness
NOTICE: Unless otherwise indicated, all documents
cited shall be the latest published versions.
4 Terminology
4.1 Definitions of terms related to silicon wafer
technology are given in ASTM Terminology F 1241.
4.2 Definitions for some additional terms are given in
SEMI M1.
4.3 The following definitions apply in the context of
this specification:
4.4 Definitions
4.4.1 furnace and thermal processes — wafers
intended for use in evaluating metal contamination in
thermal process.
4.4.2 hand scribe mark — any marking, usually on the
back surface of a wafer, scratched manually into the
silicon surface, as with a diamond-tipped scribe, for
purposes of wafer identification.
4.4.3 lithography and patterning — wafers intended
for use in evaluating pattern resolution.
4.4.4 particle counting — wafers intended for use in
evaluating the particulate contamination added by a
process tool. LLSs (Localized Light Scatterers) include
particles and COP (Crystal Originated Pits).
4.4.5 premium wafer — a silicon wafer suitable for
particle counting, metal contamination monitoring, and
measuring pattern resolution in the photolithography
process. The premium wafer has tighter specification
values in some specific items for the specific usage, and
looser or equal specification values for other items than
a prime wafer has.
5 Ordering Information
5.1 Purchase orders for silicon premium wafers
furnished to this specification shall include the items
from the appropriate specification groups listed in
Table 1.
Table 1 Wafer Classifications
Classification Application
Particle Counting Particle counting
Furnace and Thermal
Process
Metal contamination monitoring
Lithography and Patterning Measurement of pattern
resolution in photolithography
SEMI M24-1103 © SEMI 1994, 2003 4
5.2 Items which may be specified when ordering
silicon wafers are listed in attached specification tables.
Not all of these items are required for ordering
premium wafers.
6 Dimensions and Permissible Variations
6.1 The material shall conform to the dimensions and
dimensional tolerances in attached specification tables.
7 Materials and Manufacture
7.1 The material shall consist of wafers from crystals
grown by the process specified in the purchase order or
contract.
8 Physical Requirements
8.1 The material shall conform to the details specified
in the purchase order.
9 Sampling
9.1 Unless otherwise specified, ASTM Practice E 122
shall be used. When so specified, appropriate sample
sizes shall be selected from each lot in accordance with
ANSI/ASQC Z1.4. Each quality characteristic shall be
assigned an acceptable quality level (AQL) and lot total
percent defective (LTPD) value in accordance with
ANSI/ASQC Z1.4 definitions for critical, major, and
minor classifications. If desired and so specified in the
contract or order, each of these classifications may
alternatively be assigned cumulative AQL and LTPD
values. Inspection levels shall be agreed upon between
the supplier and the purchaser.
10 Test Methods
10.1 Table 1 of SEMI M18 contains a complete listing
of ASTM, DIN, and JEIDA/JIS test methods that may
apply to the testing of specified premium silicon
wafers. These attributes are listed in the order they are
found in the specification (which corresponds to the
order in SEMI M18).
10.2 Conductivity Type — Use any of the methods in
ASTM Test Methods F 42, JIS H 0607, or DIN 50432
for confirming the conductivity type of silicon wafers
covered by this specification.
10.3 Dopant — Confirm the dopant of high resistivity
silicon by the photoluminescence method of ASTM
Test Method F 1389 or by the low-temperature infrared
method of ASTM Test Method F 1630 or DIN 50438/3.
10.4 Resistivity — Determine the electrical resistivity
of the wafer in accordance with ASTM Test Method F
673 or DIN 50445 (eddy current), or ASTM Test
Method F 84, JIS H 0602, or DIN 50431 (four point
probe) using a suitable fixture to hold the wafer.
10.5 Carrier Recombination Lifetime — Determine in
accordance with F 1535 or JEIDA 53.
10.6 Oxygen Content — Determine the interstitial
oxygen content of wafers with resistivity greater than a
few ohm-cm by infrared absorption. ASTM Test
Method F 1188 is the method that was used in
analyzing the results of the international round robin
experiment that established the IOC-88 conversion
coefficient. DIN 50438/1 provides improved procedures
of correcting for back surface roughness and multiple
internal reflections. ASTM Test Method F 1619, based
on work carried out in JEIDA (JEIDA 61) and SEMI
Japan, is an alternative procedure for significantly
reducing errors associated with these two phenomena.
10.7 Carbon Content — For all but very heavily doped
epitaxial substrates, establish the carbon content in
accordance with ASTM Test Method F 1391, JEIDA
56, or DIN 50438/2.
10.8 Total Bulk Iron — No standardized test method
exists for direct determination of total bulk iron content
in silicon. ASTM Test Method F 978 can be used for
direct determination of the electrically active iron.
Extensions of the surface photovoltage method (ASTM
Test Method F 391) and of the microwave lifetime
method (ASTM Test Method F 1535) have been
reported in the literature to provide information on total
bulk iron content of boron-doped silicon; both these
extensions are based on the iron-boron pairing process.
10.9 Structural Characteristics — When feasible
observe crystal defects such as dislocation etch pits,
slip, lineage, twins, etc., in accordance with ASTM Test
Method F 1725, JIS H 0609, or DIN 50434. These
methods are destructive, and with the exception of JIS
H 0609 are based on chromium-containing etchants.
Some structural defects, especially slip, can be
determined nondestructively by means of X-ray
topographic analysis in accordance with DIN 50443/1.
Swirl and oxidation induced stacking faults (OSFs) are
best observed after heat treatment such as those
specified in ASTM Practice F 1726. However, the heat
cycles in this practice were developed for 100 mm
wafers and are not suitable for 300 mm wafers.
Accordingly, thermal cycles used shall be agreed upon
between supplier and purchaser. For observation of
OSFs, a 2-hour heat treatment at 1100°C in steam is
recommended. Observe shallow pits in accordance with
ASTM Practice F 1049.
10.10 Diameter — Diameter may be determined in
accordance with ASTM Test Method F 613 or DIN
50441/4. Because notched wafers do not have flats, it is
not necessary to make the measurements along the
particular diameters identified in ASTM Test Method F
613; rather it is suggested that measurements be made
SEMI M24-1103 © SEMI 1994, 2003 5
along the diameter perpendicular to the <100>
orientation fiducial axis (0° in the coordinate system
specified in SEMI M20), the diameter 120° counter-
clockwise, and the diameter 240° counterclockwise.
However, a more precise method of determining the
diameter is to find the circle that best fits the circum-
ference of the wafer by a least squares method; the
diameter of the wafer is twice the radius of this circle.
10.11 Flat Orientation — Determine in accordance
with ASTM Test Method F 847.
10.12 Flat Length — Determine in accordance with
ASTM Test Method F 671.
10.12.1 If flat diameter is specified instead of flat
length, determine in accordance with Section 5.2.1 of
DIN 50441/4 or by a dial gauge method (see NOTE 8)
as agreed upon between supplier and purchaser.
10.13 Notch Dimension — Determine the depth and
angle of the fiducial notch in accordance with ASTM
Test Method F 1152 with the use of a wafer holding
fixture appropriate for silicon wafers.
10.14 Notch Orientation — No test method for
verifying the crystal axis of the orientation fiducial axis
of notched wafers has yet been standardized.
Accordingly, test procedures for making this
determination shall be agreed upon between supplier
and purchaser. A starting point may be an extension of
ASTM Test Method F 847 with fixturing appropriate to
notched wafers.
10.15 Edge Profile Shape — Determine the suitability
of the edge profile in accordance with ASTM Test
Method F 928 or DIN 50441/2.
10.16 Edge Surface Finish — Establish the surface
finish of the edge region of the wafer by a method
agreed upon between supplier and purchaser.
10.17 Thickness, Center Point — Determine thickness,
center point may in accordance with ASTM Test
Method F 533, JIS H 0611, or DIN 50441/1; special
jigs or fixtures may be needed to allow the probe to
reach the center point of the wafer.
10.18 Total Thickness Variation — Determine in
accordance with ASTM Test Method F 533, ASTM
Test Method F 657, DIN 50441/1, and JIS H 0611.
NOTE 2: ASTM Test Method F 533, DIN 50441/1, and JIS
H 0611 are all 5-point methods, while Test Method F 657
involves a continuous scan pattern. JIS H 0611 differs from
ASTM Test Method F 533 and DIN 50441/1 in that the
measurements in JIS H 0611 are taken at the center and at 5
mm from the edge on diameters parallel and perpendicular to
the major flat, while the measurements in the latter two test
methods are taken at the center and at the same radial distance
(R nominal - 6 mm) on diameters 30 degrees and 120 degrees
counterclockwise from the bisector to the primary flat or
notch (with the wafer facing front surface up).
10.19 Surface Orientation — Determine the crystal-
lographic orientation of the wafer surface in accordance
with ASTM test methods F 26, JEIDA Method 18, or
DIN 50433 using a suitable fixture to hold wafer.
10.20 Bow and Warp — Determine bow in accordance
with ASTM Test Method F 534 and warp in accordance
with ASTM Test Method F 1390 or Test Method F 657.
NOTE 3: ASTM has standardized two methods for
measuring warp. ASTM Test Method F 1390 is an automated,
non-contact method which provides for correction of the
wafer deflection due to gravitational effects. The scan pattern
covers the entire fixed quality area. ASTM Test Method F
657 is a manual, non-contact method which has a continuous,
prescribed scan pattern which covers only a portion of the
wafer surface. There is no provision for correction of the
wafer deflection due to gravitational effects. As noted in
Appendix 2, different reference planes are used for the two
methods. Because Test Method F 657 employs a back surface
reference plane, the measured warp may include contributions
from thickness variation of the wafer. Test Method F 1390
employs a median surface reference plane and is not
susceptible to interferences from thickness variations. In
general, Test Method F 1390 is preferred, especially for
wafers 150 mm in diameter and larger, although ASTM Test
Method F 1530 may also be used for this determination.
10.21 Sori — If sori is specified in lieu of bow or warp
or both, determine by a method agreed upon between
the supplier and the purchaser.
NOTE 4: Because sori is a property of the top surface of an
unclamped wafer, it may be measured on many types of
flatness measuring instruments. ASTM Test Method F 1451
may, in principle, be used for determination of sori.
10.22 Flatness — Determine by a method agreed upon
between the supplier and the purchaser. It is
recommended that site flatness is determined in
accordance with ASTM Test Method F 1530 using a
site-by-site front surface reference (indicated by the
acronym SFQR in the Flatness Decision tree (see SEMI
M1, Figure A1-1)). The percent usable area (PUA) shall
be calculated as the percentage of the total number of
full sites within the FQA that meet the specification.
10.23 Surface Metal Contamination — Determine
surface metal contamination by a method agreed upon
between supplier and purchaser; ASTM Test Method F
1617 is suitable for sodium and aluminum, and ASTM
Test Method F 1526 is suitable for chromium, iron,
nickel, copper, and zinc at the specified levels. Other,
more sensitive methods may also be utilized by
agreement between supplier and purchaser.
10.24 Back Surface Gloss — Determine test method in
accordance with ASTM D523 or JIS Z8741 using a 60
degree of incidence and referencing the zero to a mirror