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SEMI G80-0200 © SE MI 2000 28 Example A 2-5 Test Method Sum mar y for Showing Data Entry to Table 2 for OTA Calculation LEVEL 1 Tim in g Linearit y Ext. Dly. / Mult Period Data below represents Level 1 e dge-d elay resul…

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SEMI G80-0200 © SEMI 200027
Drive to Compare Edge Error
Compare Error
MIN Value- MIN is the value
all comparators are
programmed to when the first
drive edge is detected.
For a sweep- Compare edges
should be programmed far in
advance of the reference signal
allowing enough room to detect
the earliest occurrence of a drive
edge.
TIMING RELATIONSHIPS, DEFINITIONS & EXAMPLE RESULTS
DEFINITIONS-
Reference- The programmed value of the drivers
Drive to Compare Error- The difference between the average of min & max for Drive and the
average of min & max for Compare error.
RELATIONSHIPS & EXAMPLE RESULTS-
Negative Error: Reference - Min Value = 1000ps - 750ps = 250ps
Positive Error: Reference - Max Value = 1000ps - 1350ps = -350ps
Drive to Compare Error: Reference - [(Min Value + Max Value)/2] = 1000ps - [(750ps + 1350ps )/2] = -50ps
For a sweep- Compare edges
should be programmed fa
r
b
eyond the reference signal
allowing enough room to
detect the latest occurrence
of a drive edge.
MAX drive value- Detect the
latest occurrence of the drive
edge with the earliest compare
edge (last fail- Timing Linearity
Test 10.2.1)
MIN drive value- Detect the earliest
occurrence of the drive edge with the
latest compare edge (first pass- Timing
Linearity Test 10.3.1)
50ps
In this example:
Drive edge error = ±200ps
Compare edge error = ±100ps
Drive to Compare error = - 50ps
This example will illustrate how
numerical error values are obtained.
MAX Value- MAX is the value
all comparators are programmed
to when the last drive edge is
detected.
1350ps
(Max Value)
750ps
(Min value)
Sweep
Compare Edges
N
OTE: All drive edges are
detected in parallel in pairs:
pin 1 & 2, 3 & 4,...n-1 & n.
N
OTE: All drive edges are
detected in parallel in pairs: pin 1
& 2, 3 & 4,...n-1 & n.
850ps
1050ps
950ps
1000ps Reference
50ps
750ps
First Pass
Min value
Last Fail
Max value
When the edges on all pins are
detected the drive to compare
error relationship will appear as
indicated here with associated
error values indicated.
-100ps +100ps
-100
p
s
+100ps
-100ps +100ps
-200ps
Drive Edges
1000ps Drive
Reference
+200ps
-200ps
Drive Edges
1000ps Drive
Reference
+200ps
-200ps +200ps
1000ps
1350ps
800ps
-200ps
+200ps
Drive Error
Drive
Reference
Last fail
Sweep
+100ps-100ps
First pass
0
n
s
750ps
0ns
12000ps
Drive
Reference
Compare Edges
1350ps
Figure A2-4
Drive Edge Error >> Compare Edge Error
SEMI G80-0200 © SEMI 2000 28
Example A2-5 Test Method Summary for Showing Data Entry to Table 2 for OTA Calculation
LEVEL 1
Timin
g
Linearit
y
Ext. Dly. / Mult Period
Data below represents
Level 1 edge-delay
results
LEVEL 2
Hi
g
h S
p
eed Clock
Accuracy
_
_________________
_
Drive Input Z Timing
Error Level 1
(Section 10.3.5) Z to
0 (Low)
Timing Linearity
Level 1 (Sec.10.3.1)
Positive Error:
+250
Negative Error:
–350
b) High Speed Clock
Transition Time
Variation Level 2
(Section 10.4.3- Drive
Input Transition Time
for clock function)
a) High Speed Clock
Delay Error
Level 2 (Section 10.4.1-
Drive Input Timing
Delay for clock
function)
Extended Delay
Level 1 (Sec. 10.3.4)
Positive Error:
Negative Error:
Multiple Period
Level 1 Optional
(Sec. 10.3.6)
Positive Error:
Negative Error:
Drive Input Z Timing
Error Level 1
(Section 10.3.5) Z to
1 (High)
Drive Input Z Timing
Error Level 1
(Section 10.3.5) 0
(Low) to Z
Drive Input Z Timing
Error Level 1
(Section 10.3.5) 1
(High) to Z
1) Drive In
p
ut To
Compare Output
Timing
–50
3) Com
p
are Out
p
ut
Edge Placement
±100
2) Drive
Input Edge
Placement
±200
Drive Input to
Compare Out put
Timing Accuracy
Taken from 10.3.1
–50
a) Compare Output
Time Delay Error
Level 2 (Section
10.4.2)
±100
a) Drive Input Timing
Delay Error Level 2
(Section 10.4.1)
±200
b) Drive Input
Transition Time
Variation
Level 2 (Section
10.4.3)
c) Drive Input Timing
Cycle Jitter Level 2
(Section 10.4.4)
Single Point Overall Timing Accuracy (OTA) Results
D
ata to enter here is: A = Dr (item 2) + Cmp (item 3) + Dr-Cmp (item 1)
-B = -Dr (item 2) - Cmp (item 3) + Dr-Cmp (item 1)
.
+250ps, –350ps
Drive Z Timin
g
Data below
represents Level 1 Z-
state timing results
c) High Speed Clock
Cycle Jitter Level 2
(Section 10.4.5)
d) High Speed Clock
Phase Jitter Level 2
(Section 10.4.6)
The user of the method is advised to read Section 13,
Precautions before filling in this table.
-200ps
Drive Edges
1000ps
+200ps
OTA Calculation:
OTA = A, -B
A = Dr + Cmp + Dr-Cmp
200 + 100 + (-50) = 250
-B = -Dr - Cmp + Dr-Cmp
-200 - 100 + (-50) = -350
OTA = 250ps, -350ps
950ps
OTA DATA CALCULATION and
TABLE 2 ENTRY EXAMPLE
800ps 1200ps
Drive edges programmed
value of 1000ps
+100ps-100ps
Compare Edges
B- Latest drive to earliest compare: -350ps
-50ps
B
A- Earliest drive to latest compare: 250ps
Compare edges programmed
value of 1000ps
A
850ps 1050ps
250ps
-350ps
SEMI G80-0200 © SEMI 200029
Example A2-6 Test Method Summary for Showing Data Entry to Table 2 for OTA Calculation
LEVEL 1
Timin
g
Linearit
y
Ext. Dly. / Mult Period
Data below represents
Level 1 edge-delay
results
LEVEL 2
Hi
g
h S
p
eed Clock
Accuracy
_
_________________
_
Drive Input Z Timing
Error Level 1
(Section 10.3.5) Z to
0 (Low)
Timing Linearity
Level 1 (Sec.10.3.1)
Positive Error:
+350
Negative Error:
–250
b) High Speed Clock
Transition Time
Variation Level 2
(Section 10.4.3- Drive
Input Transition Time
for clock function)
a) High Speed Clock
Delay Error
Level 2 (Section 10.4.1-
Drive Input Timing
Delay for clock
function)
Extended Delay
Level 1 (Sec. 10.3.4)
Positive Error:
Negative Error:
Multiple Period
Level 1 Optional
(Sec. 10.3.6)
Positive Error:
Negative Error:
Drive Input Z Timing
Error Level 1
(Section 10.3.5) Z to
1 (High)
Drive Input Z Timing
Error Level 1
(Section 10.3.5) 0
(Low) to Z
Drive Input Z Timing
Error Level 1
(Section 10.3.5) 1
(High) to Z
1) Drive In
p
ut To
Compare Output
Timing
+50
3) Com
p
are Out
p
ut
Edge Placement
±100
2) Drive
Input Edge
Placement
± 200
Drive Input to
Compare Out put
Timing Accuracy
Taken from Section
10.3.1
+50
a) Compare Output
Time Delay Error
Level 2 (Section
10.4.2)
± 100
a) Drive Input Timing
Delay Error Level 2
(Section 10.4.1)
± 200
b) Drive Input
Transition Time
Variation
Level 2 (Section
10.4.3)
c) Drive Input Timing
Cycle Jitter Level 2
(Section 10.4.4)
Single Point Overall Timing Accuracy (OTA) Results
D
ata to enter here is: A = Dr (item 2) + Cmp (item 3) + Dr-Cmp (item 1)
-B = -Dr (item 2) - Cmp (item 3) + Dr-Cmp (item 1)
.
+350ps, –250ps
Drive Z Timin
g
Data below
represents Level 1 Z-
state timing results
c) High Speed Clock
Cycle Jitter Level 2
(Section 10.4.5)
d) High Speed Clock
Phase Jitter Level 2
(Section 10.4.6)
The user of the method is advised to read Section 13,
Precautions before filling in this table.
-200ps
Drive Edges
1000ps
+200ps
OTA Calculation:
OTA = A, -B
A = Dr + Cmp + Dr-Cmp
200 + 100 + 50 = 350
-B = -Dr - Cmp + Dr-Cmp
-200 - 100 + 50 = -250
OTA = 350, –250
1050ps
OTA DATA CALCULATION and
TABLE 2 ENTRY EXAMPLE
800ps 1200ps
Drive edges programmed
value of 1000ps
+100ps-100ps
Compare Edges
B- Latest drive to earliest compare: -250ps
50ps
B
A- Earliest drive to latest compare: 350ps
Compare edges programmed
value of 1000ps
A
950ps 1150ps
350ps
-250ps