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SEMI M41-1101 © SE MI 2000, 2001 2 F1188 — Standard Test Method for Interstitial Atomic Oxygen Content of Silico n by Infrared Absorption F1241 — Standard Term inology of Silicon Technology F1390 — Standard Test Method f…

SEMI M41-1101 © SEMI2000, 20011

SEMI M41-1101

SPECIFICATION OF SILICON-ON-INSULATOR (SOI) FOR POWER

DEVICE/ICs

This specification was technically approved by the Global Silicon Wafer Committee and is the direct

responsibility of the Japanese Silicon Wafer Committee. Current edition approved by the Japanese Regional

Standards Committee on August 3, 2001. Initially available at www.semi.org August 2001; to be published

November 2001. Originally published June 2000; previously published July 2001.

1 Purpose

1.1 This specification covers requirements for silicon-

on-insulator (SOI) for semiconductor power-device/IC

manufacture. By defining inspection procedures and

acceptance criteria, both users and suppliers may define

product characteristics and quality requirements.

2 Scope

2.1 This specification provides requirements of SOI

wafers, which are used for power devices/ICs of

specific voltage applications. The voltage ranges cover

low voltage (40–60V), medium voltage (150–250V)

and high voltage (500–600V). The specification covers

physical, electrical, and surface parameters pertinent to

bonded wafers.

2.2 Included in this document is a list of goals for

inspection of these wafers which need to be negotiated

between the users and suppliers of bonded wafers.

2.3 This standard does not purport to address safety

issues, if any, associated with its use. It is the

responsibility of the users of this standard to establish

appropriate safety and health practices and determine

the applicability of regulatory limitations prior to use.

3 Referenced Standards

3.1 SEMI Standards

SEMI M1 — Specifications for Polished

Monocrystalline Silicon Wafers

SEMI M2 — Specifications for Silicon Epitaxial

Wafers

SEMI M18 — Format for Silicon Wafer Specification

Form for Order Entry

SEMI M34 — Guide for Specifying SIMOX Wafers

3.2 ASTM Standards

F26 — Standard Test Methods for Determining the

Orientation of a Semiconductive Single Crystal

1 American Society for Testing and Materials, 100 Barr Harbor

Drive, West Conshohocken, Pennsylvania 19428-2959, USA.

Telephone: 610.832.9585, Fax: 610.832.9555. Website:

www.astm.org

F42 — Standard Test Methods for Conductivity Type

of Extrinsic Semiconducting Materials

F43 — Standard Test Methods for Resistivity of

Semiconductor Materials

F81 — Standard Test Method for Measuring Radial

Resistivity Variation on Silicon Wafers

F84 — Standard Test Method for Measuring Resistivity

of Silicon Wafers with an In-Line Four-Point Probe

F110 — Standard Test Method for Thickness of

Epitaxial or Diffused Layers in Silicon by the Angle

Lapping and Staining Technique

F154 — Standard Practices and Nomenclature for

Identification of Structures and Contaminants Seen on

Specular Silicon Surfaces

F399 — Standard Test Method for Thickness of

Heteroepitaxial or Polysilicon Layers

F523 — Standard Practice for Unaided Visual

Inspection of Polished Silicon Wafer Surfaces

F533 — Standard Test Method for Thickness and

Thickness Variation of Silicon Wafers

F576 — Standard Test Method for Measurement of

Insulator Thickness and Refractive Index on Silicon

Substrates by Ellipsometry

F613 — Standard Test Method for Measuring

Diameter of Semiconductor Wafers

F671 — Standard Test Method for Measuring Flat

Length on Wafers of Silicon and Other Electronic

Materials

F847 — Standard Test Methods for Measuring

Crystallographic Orientation of Flats on Single Crystal

Silicon Wafers by X-Ray Techniques

F928 — Standard Test Methods for Edge Contour of

Circular Semiconductor Wafers and Rigid Disk

Substrates

F1152 — Standard Test Method for Dimensions of

Notches on Silicon Wafers

F1153 — Standard Test Method for Characterization of

Metal-Oxide-Silicon (MOS) Structures by Capacitance-

Voltage Measurements

SEMI M41-1101 © SEMI 2000, 2001 2

F1188 — Standard Test Method for Interstitial Atomic

Oxygen Content of Silicon by Infrared Absorption

F1241 — Standard Terminology of Silicon Technology

F1390 — Standard Test Method for Measuring Warp

on Silicon Wafers by Automated Noncontact Scanning

F1391 — Standard Test Method for Substitutional

Atomic Carbon Content of Silicon by Infrared

Absorption

F1526 — Standard Test Method for Measuring Surface

Metal Contamination on Silicon Wafers by Total

Reflection X-Ray Fluorescence Spectroscopy

F1527 — Standard Guide for Application of Silicon

Standard Reference Materials and Reference Wafers for

Calibration and Control of Instruments for Measuring

Resisitivity of Silicon

F1530 — Standard Test Method for Measuring

Flatness, Thickness, and Thickness Variation on Silicon

Wafers by Automated Noncontact Scanning

F1535 — Standard Test Method for Carrier

Recombination Lifetime in Silicon Wafers by

Noncontact Measurement of Photoconductivity Decay

by Microwave Reflectance

F1617 — Standard Test Method for Measuring Surface

Sodium, Aluminum, Potassium, and Iron on Silicon and

EPI Substrates by Secondary Ion Mass Spectroscopy

F1619 — Standard Test Method for Measurement of

Interstitial Oxygen Content of Silicon Wafers by

Infrared Absorption Spectroscopy with p-Polarized

Radiation Incident at Brewster Angle

F1620 — Standard Practice for Calibrating a Scanning

Surface Inspection System Using Monodisperse

Polystyrene Latex Spheres Deposited on Polished or

Epitaxial Wafer Surfaces

F1726 — Standard Guide for Analysis of

Crystallographic Perfection of Silicon Wafers

F1727 — Detection of Oxidation Induced Defects in

Polished Silicon Wafers

3.3 ANSI Standard

ANSI/ASQC Z1.4 — Sampling Procedures and Tables

for Inspection by Attributes

2 American Society for Quality Control, 611 East Wisconsin

Avenue, Milwaukee, WI 53202

3.4 JEITA Standard

JEIDA 50 — Standard Specification for SOI Wafers

NOTE 1: Unless otherwise indicated, all documents cited

shall be the latest published versions.

4 Terminology

4.1 Many terms relating to silicon technology are

defined in ASTM Terminology F1241, “Terminology

of Silicon Technology.”

4.2 Other terms are defined as follows:

4.2.1 base silicon wafer — the silicon wafer below the

insulator layer, supporting the top silicon film.

4.2.2 bonded wafers — defined as two silicon wafers

bonded together with an insulating layer. This insulator

layer is typically thermally grown silicon-dioxide.

4.2.3 bonding interface — the plane where the bonding

between the two wafers takes place.

4.2.4 buried oxide layer (BOX) — the insulator layer

between the two wafers when the insulator layer is

silicon-dioxide.

4.2.5 non-SOI edge area — an annulus between the

nominal radius of the surface silicon layer and the

nominal radius of the base silicon wafer (for bonded

SOI wafers). The annulus which implies an area is

determined by its width as one dimension. It is the

difference in the nominal radius of the surface silicon

layer and that of the base silicon wafer.

4.2.6 thickness of top silicon film — the distance

between the surface of the top silicon film and the top

silicon film-buried oxide interface.

4.2.7 top silicon film — the silicon layer on top of the

insulator film in which the semiconductor active

devices are fabricated.

4.2.8 void — the absence of a chemical bond at the

bonding interface.

5 Ordering Information

5.1 Purchase orders for bonded wafers furnished to this

specification shall include the following items:

5.1.1 Substrate Characteristics for the device layer

(diameter, dopant, orientation, resistivity, Oi, etc.)

5.1.2 Substrate Characteristics for the base wafer

(diameter, thickness, dopant, orientation, resistivity,

etc.)

3 Japanese Electronic and Information Technology Industries

Association, Tokyo Chamber of Commerce and Industry Bldg. 2-2,

Marunouchi 3-chome, Chiyoda-ku, Tokyo 100-0005, Japan. Website:

www.jeita.or.jp

SEMI M41-1101 © SEMI2000, 20013

5.1.3 Buried oxide thickness and thickness tolerances

5.1.4 Top silicon film thickness and thickness

tolerances

5.1.5 Warp limits

5.1.6 Top silicon film OSF defect limits

5.1.7 Top silicon film carrier life time limits

5.1.8 Buried oxide defect limits

5.1.9 Edge profile of the top silicon film and non-SOI

edge area

5.1.10 Rotation alignment between top silicon film and

the base silicon

5.1.11 Position of the bonding interface

5.1.12 Methods of test and measurements (see

Sections 8 and 9)

5.1.13 Lot acceptance procedures (see Section 7)

5.1.14 Certification (if required)

5.1.15 Packing and marking (see Section 10)

NOTE 2: Verification test procedures of certification of these

items shall be agreed upon between the users and the supplier

(see Sections 8 and 9).

6 Requirements

6.1 The complete specifications for Overall Wafer, Top

Silicon Film, Buried Oxide (BOX) and Base Silicon

Wafer are listed in Tables 1 to 5.

Table 1 Silicon-on-Insulator (SOI) Specifications for Low Voltage (45–60V) Power Device (1)

Parameters (Units) Value ASTM Test Method or

Measurement Procedure

Acceptance

Wafer(Overall)

Diameter (mm) 125, 150, 200 F613-93 Note A

Thickness (µm) (Value of regular silicon

wafer) + (SOI thickness) +

(Box thickness)

F533-96, F1530-94 Note A

Total Thickness Variation (µm) Note C F1530-94 Note C

LTV (µm) Note C F1530-94 Note C

Warp (µm) ≤ 100 (Note B, C, F) F1390-92 Note C, or Certified by

Wafer Manufactures

Non-SOI Edge Area (mm) ≤ 3 (Note C) Optical Metrology Note C, or Certified by

Wafer Manufactures

Edge Profile/Edge Profile

Surface Finish

Note C F928-93 Note C, or Certified by

Wafer Manufactures

Top Silicon Film

Thickness (µm) 2–12 Note D

(F399-88)

Note C, E,

Must be measured on each

wafer

Surface Orientation Note C X-ray Diffraction

(F26-87a)

Note C, or Certified by

Wafer Manufactures

Resistivity (ohm-cm) Note C F43-93, F84-93,

F1527-94

Note C, or Certified by

Wafer Manufactures

Conductivity Type Note C F42-93 Note C, or Certified by

Wafer Manufactures

Oxygen Concentration (/cm

) Note C F1188-93a,

F1619-95

Note C, or Certified by

Wafer Manufactures

Carbon Concentration (/cm

) Note C F1391-93 Note C, or Certified by

Wafer Manufactures

Surface Cleanliness: Metal

Contamination (/cm

)

Note A, C AAS, ICP-MS,

TXRF (F1526-95),

SIMS (F1617-98)

Note A, C

Surface Cleanliness: Particle

Density (/wafer)

Note A, C Light Scattering

Tomography (F1620-96)

(SEMI M34)

Note A, C