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SEMI M60-0305 © SEMI 2005 3 3.3 EIA/JEDEC Standards 2, 3 EIA/JEDEC 35 — Procedure for the Wafe r-Level Testing of Thin Diel ectrics EIA/JEDEC 35-1 — General Guidelines for Designing Te st Structures for the Wafer-Level T…

SEMI M60-0305 © SEMI 2005 2

TDDB method can be used as an evaluation of gate oxide lifetime. In this test method, the constant-current TDDB

method is chosen, because the constant current TDDB method has less influence on parasitic resistance in a

measurement circuit than the constant-voltage TDDB method.

2.5 This test method gives instructions for the procedure for characterizing mirror-polished, p-type CZ silicon

wafers. Gate electrodes were negatively biased so that the silicon surface is in accumulation. Stress current shall be

sufficient for the gate oxide to be broken down within a finite measurement time. In addition, it is desirable to have

an applied current density J within 0.01 and 0.1A/cm

2.6 The stress gate current has to be reversed for the n-type silicon wafer.

2.7 The poly-silicon film is used as gate electrode of measured MOS capacitors. The poly-silicon film can make

standard test results applicable to the testing of wafers used to fabricate integrated circuits rather than other metal

electrodes because poly-silicon electrodes are commonly used in actual devices. However, a gate electrode other

than poly-silicon gate electrode shall be studied for applications in advanced ultralarge-scale integrated circuits. In

this case, the new electrode material shall have the same detection sensitivity to silicon wafer defects as poly-silicon

electrode.

NOTICE: This test method does not purport to address safety issues, if any, associated with its use. It is the

responsibility of the users of this test method to establish appropriate safety and health practices and determine the

applicability of regulatory or other limitations prior to use.

3 Referenced Standards

NOTE 1: When there is no special direction, all the quoted documents are the newest editions.

NOTE 2: When a material other than poly-silicon is used for electrodes, refer to the standard suitable for individual process.

3.1 SEMI Standards

SEMI C3.6 — Standard for Phosphine (PH

) in Cylinders, 99.98% Quality

SEMI C3.54 — Gas Purity Guideline for Silane (SiH

)

SEMI C21 — Specifications and Guideline for Ammonium Hydroxide

SEMI C27 — Specifications and Guidelines for Hydrochloric Acid

SEMI C28 — Specifications and Guidelines for Hydrochloric Acid

SEMI C30 — Specifications and Guidelines for Hydrogen Peroxide

SEMI C35 — Specifications and Guideline for Nitric Acid

SEMI C38 — Guideline for Phosphorus Oxychloride

SEMI C41 — Specifications and Guidelines for 2-Propanol

SEMI C44 — Specifications and Guidelines for Sulfuric Acid

SEMI C54 — Specifications and Guidelines for Oxygen

SEMI C59 — Specifications and Guidelines for Nitrogen

SEMI M1 — Specifications for Polished Monocrystalline Silicon Wafers

SEMI M51 — Test Method For Characterizing Silicon Wafers by Gate Oxide Integrity.

SEMI MF1241 — Terminology of Silicon Technology (Reapprpved2000)

SEMI MF1771 — Standard Test Method for Evaluating Gate Oxide Integrity by Voltage Ramp Technique

3.2 ASTM Standards

ASTM D5127 — Standard Guide for Ultra Pure Water Used in the Electronics and Semiconductor for Industry.

1 American Society for Testing and Materials, 100 Barr Harbor Drive, West Conshohocken, Pennsylvania 19428-2959, USA. Telephone:

610.832.9585, Fax: 610.832.9555 Website: www.astm.org

SEMI M60-0305 © SEMI 2005 3

3.3 EIA/JEDEC Standards

2, 3

EIA/JEDEC 35 — Procedure for the Wafer-Level Testing of Thin Dielectrics

EIA/JEDEC 35-1 — General Guidelines for Designing Test Structures for the Wafer-Level Testing of Thin

Dielectrics

EIA/JEDEC 35-2 — Test Criteria for the Wafer-Level Testing of Thin Dielectric

NOTICE: Unless otherwise indicated, all documents cited shall be the latest published versions.

4 Terminology

4.1 Abbreviations & Acronyms

4.1.1 COP — Crystal Originated Particles

4.1.2 GOI — Gate Oxide Integrity

4.1.3 LOCOS — Local Oxidation of Silicon

4.1.4 MOS — Metal Oxide Semiconductor

4.1.5 STI — Shallow Trench Isolation

4.1.6 TZDB — Time Zero Dielectric Breakdown

4.2 Definitions

4.2.1 Many terms relating to silicon technology are defined in SEMI MF1241.

4.2.2 Definitions for some additional terms are given in SEMI M1 and SEMI MF1771.

4.2.3 Other terms are defined as follows:

4.2.3.1 Crystal Originated Particles

(COP) — This is the one of grown-in defects in the CZ Si wafers with an

octahedral structure. This was found as particles appeared on the silicon surface by repetition SC-1

of RCA

cleaning.

4.2.3.1.1 Discussion — It has been thought that the COP is one of the main origins of the GOI. The gate oxide

formed on the Si surface at which the COP appears easily breaks down at the corner of the octahedral shape like at a

Si trench corner

6,7,8

. This corner of octahedral structures is thinning the oxide films. The oxide electric field

enhances at that place. The breakdown electric field is decreased.

4.2.3.2 Failure Modes — The TDDB Weibull plot

9, 10

is classified to three modes. A typical plot is shown in

Figure 1.

Accidental failure A-A mode

A-B mode

Wearout breakdown W mode

2 Electronic Industries Alliance, EIA Engineering Department, Standards Sales Office, 2001 Eye Street, NW, Washington, D.C. 20006, USA.

Website: www.eia.org

3 Joint Electron Device Engineering Council, 2500 Wilson Blvd., Arlington, VA 22201, website: www.jedec.org

4 J. Ryuta, E. Morita, T. Tanaka and Y. Shimanuki, “Crystal – Originated Singularities on Si Wafer Surface after SC1 Cleaning”, Jpn. J.

Appl. Phys. 29(1990) L947.

5 W. Kern and D. Puotinen, “Clean Solution Based on Hydrogen Peroxide for Use in Silicon Semiconductor Technology”, RCA Rev., 31,

187(1970).

6 T. Mera, J. Jablonski, K. Nagai, and M. Watanabe, “Grown-in defects in silicon crystals responsible for gate oxide integrity deterioration”,

Ohyo-Buturi, 66(7), 728 (1997).

7 K.Yamabe and K.Imai,”Nonplanar Oxidation and Reduction of Oxide Leakage Currents at Silicon Corners by Rounding-off Oxidation”, IEEE

Trans. Electron Devices, ED–34, 1681(1987).

8 K.Yamabe, Y.Shimada, M.Piao, T.Yamazaki, T.Otsuki, R.Takeda, Y.Ohta, S.Jimbo, and M.Watanabe, “Effect of SiO

Thickness on Dielectric

Breakdown Defect Density Due to Surface Crystal–Originated Particles”, J.Electrochem.Soc., 150, F42(2003).

9 D. L. Crook, “Method of Determining Reliability Screens for Time Dependent Dielectric Breakdown”, Proc. Int. Reliability Physics

Symposium, 1979, p.1.

10 E. S. Anolick and G. R. Nelson, “Low Field Time Dependent Dielectric Integrity”, Proc. Int. Reliability Physics Symposium, 1978, p.8.

Figure 1

Classification in Weibull plot of TDDB result.

4.2.3.2.1 Discussion on failure modes:

 A-A Mode: Initial breakdown failure

o This failure is caused by defects generated during gate oxide formation process such as pinholes and also

by crystal defects such as COPs. This failure corresponds to the A mode and partly B mode failures of

TZDB.

 A-B Mode: Intermediate breakdown failure

o This failure is caused by extrinsic defects which are not serious enough to cause the A-A mode. This

failure corresponds to the B mode and partly C mode failure of TZDB.

 W Mode: Wearout breakdown

o This breakdown is also called intrinsic breakdown or fatigue breakdown, and relates to the intrinsic lifetime

of oxide films. The measurement of this breakdown shall be performed carefully because the result

depends on measurement conditions.

o Response rapidity of the measurement system has a great influence on A-A mode detection. The total

number of A-A and A-B mode failures is related to the crystal quality of the mirror-polished CZ Si wafers.

4.2.3.3 Categorization of Breakdown Modes — boundaries of A-A/A-B modes and A-B/W modes shall be defined

in advance.

4.2.3.3.1 A-A/A-B Mode Boundary

 The detectable minimum Q

values depend on the stress current and response speed of the measurement

systems. As stress current density increases, the charge density of the A-A/A-B mode boundary may also

increases. This effect shall be considered when defining the A-A/A-B mode boundary. Based on these round

robin results, the charge density range from 0.0001C/cm

to 0.01 C/cm

is recommended as the A-A/A-B mode

boundary.

4.2.3.3.2 A-B/W mode boundary

 The A-B/W mode boundary is defined in terms of Weibull plots as shown in Figure RI-3. Ideally, it shall be

determined by the intercept point of two approximation lines in the A-B and W mode ranges. If the boundary

charge density is too low (Q < 1 C/cm

), one part of the A-B mode breakdown can be counted as the W mode.

Otherwise, if the boundary charge density is too high (Q > 4 C/cm

), one part of the W mode breakdown can be

counted as the A-B mode.

 In both cases, we have errors in the classification of the failure mode categories, even if the measurement is

accurately carried out and appropriate Weibull plots are obtained. So, the results of this round robin indicate

that the charge density of 2 C/cm

is recommended as the A-B/W mode boundary. To measure the failure rates

at the boundary charge density of the A-B/W modes, all samples are not necessarily broken down. If the

determination procedure of the boundary charge density is clear, the application of a predetermined charge